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Adding dummy elements to the layout

May 7, 2019, 11:31 am
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Hi,

I started my layout design and for the matching purpose, I need to add dummy elements like transistors, resistors. whenever I add an instance as a dummy in the layout the LVS will complain that this element doesn't match to the schematic, Then I need to put that instance in the schematic as well, but this procedure makes my design longer.

I believe that there is some tool in Cadence Layout XL that is concerned with adding dummy elements and I hope you could help me with. Or if there is no such tool then at least how to ignore elements in the Layout from LVS

Thanks

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Is there any tips & simulator settings to accelerate tran initial converge of ams top analog&digital simulation ?

May 7, 2019, 6:31 pm
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current status: ams top  analog(schematic)&digital(rtl) simulation tran initial converge takes too long   >4hours

Is there any tips & simulator settings to accelerate tran initial converge for ams top simulation?

There are 3 tips I've already used below:

1 set initial Q value for meta-stable dff

2 set regulator initial out to its target stable voltage

3 set diff voltage H-L to oscillator's differential output

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Temperature sweep of a chopped bandgap in MonteCarlo

May 8, 2019, 1:10 am
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Hi all,

The circuit I'm simulating is a chopped bandgap reference with curvature compensation.

I'm interesting in testing the effectiveness of the curvature compensation scheme over a MonteCarlo sweep, but I'm not sure how to do this.

My current idea is that since the the circuit is chopped, For every sample I need to run a transient/pss to get the final value of the reference. Also, I would have to run such a simulation for every temperature of interest in order to build the vector containing the reference value swept vs. temperature. This seems to me a very inefficient way to solve this problem.

Perhaps you know a more efficient way to solve this problem? This has to be done in ADE-L / skill as we don't have ADE-XL licenses available.

Thanks and best regards,

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Model of Transient Noise Simulation in Cadence

May 8, 2019, 3:28 am
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Regarding the transient noise simulation in Cadence, is the generated noise behaved as additive white noise model? In time-domain, is it behaved as normal distribution with one sigma equal to the equivalent noise of the circuit and the system? We found that the simulation outputs some extreme situation even the data point is of very few. Thank you for your help.

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Save subcircuit instance nets in ADE Assembler

May 8, 2019, 7:18 am
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In ADE Explorer (and ADE-L) there is an option to save all voltages or currents within a subcircuit instance ("Outputs -> To be saved -> Select by Subckt Inst"). I can't find this feature in ADE Assembler.

My workaround is now to dive from the Assember view into the Explorer view and select this feature there. But maybe there is also a way to do this in Assembler directly?

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Maestro: Could not find state ..../spectre/active active

May 8, 2019, 11:33 pm
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Hi,

We do have 2 similar maestro views "maestro_lpe" and "maestro_sch". Both view do contain variables and outputs in the users workarea.

The user checked in the files in our revision control system SOS.

When checking out the cell by other users, the "maestro_sch" is not working. No variables and outputs are visible for other users after checkout of this cell. In the CIW the following message comes:

WARNING (ADE-1077): Could not find state /icd/sim/hflroic_g6r3/uidn5147/sos_main/sim/G6R3_tb/mm_test_sig_and_xt/maestro_sch/G6R3_tb/mm_test_sig_and_xt/spectre/active active.
WARNING (EXPLORER-1648): The 'G6R3_tb/mm_test_sig_and_xt/maestro_sch' cellview has been opened in the read-only mode.
       The setting for the number of history entries to be saved, specified using the
       Save Options form or the adexl.simulation saveLastNHistoryEntries environment
       variable, will be applied only to the histories created in this session.
       Histories saved in the previous sessions will not be removed.

When comparing the content of the view-folders of "maestro_sch" and "maestro_lpe" I see that a file "active.state" is only existing in "maestro_lpe". That is also true for the users folders - not only for the checked-out folders. But the user does see all outputs and variables.

What can be the problem here  - any idea ?

IC6.1.8.010 on RHEL6 and RHEL7

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Instalation a new component

May 9, 2019, 1:58 am
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Hello
I am Fritz Antonio and i am starting to use OrCad 16.6. I would like to instal a new component and i have donwloaded its Psice Model from the site of Texas Instriument. How can i instal, i need this component for progect, design and simulation ?
Have you a tutoria?

thanks a lot and byeee
Fritz

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ADE Assembler - Define IF statement with multiple results arguments (vector)

April 26, 2019, 1:47 am
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Hi everyone,

Could someone provide some insight how to define a global/design variable in ADE Assembler Maestro in terms of an IF statement, but instead of passing just one value after evaluating the IF condition, it provides a vector (which would result in a parametric simulation)?

Example: 

If Var2 == Value1, then Var1 takes the value set [Value-A Value-B Value-C] --> three simulations

If Var2 == Value2, then Var1 takes the value set [Value-D Value-D] --> two simulations

So far I can only make it work for the case when the value set has just one value (typical IF-ELSE). How is the proper syntax to achieve this? Is there a special function for this case?

Thanks!

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Terminal in CDF termOder is invalid (CDL netlist)

May 9, 2019, 5:56 am
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Hello all,

I'm trying to debug an annoying problem concerning the CDL netlist of a small testbench.

In netlister's log I see:

WARNING (AUCDL-43): Terminal VDD appearing in CDF termOrder for
component : ABC
in cellview : symbol
of library : XYZ
is invalid.
Ensure that this CDF has same terminal names as specified in this cell view.
Nets will be printed in default terminal order for this component.

This happens with virtuoso ICADV 12.3.500.23. That symbol view definitely has a VDD terminal and so does the schematic view.

Since this is a read-only cell for me, I cannot run a chek&save, nor can I change the data.dm file.

Do you have any advice about how to debug such problem? (e.g. why is VDD invalid)

Best regards,

Patrik

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Direct Plot then Transient Signal stop updating after some time

May 9, 2019, 9:14 am
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I am running Transient Analysis and usually after running it for some time (not finished yet) I can plot some signals from Direct Plot --> Transient Signal. However, sometimes I get a problem, at some time it plots but stop update the signals after that. For example, if I run the analysis for 1 milisecond and at 250u seconds I can plot the signals. However, for some reason it doesn't update more even the analysis already runs up to 800u seconds.  I have to wait for the transient analysis to finish or stop it to see the signals. 
What's the problem with it? 
Is there some method to fix this?

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Cannot extract spectre transient simulation data using Matlab

May 9, 2019, 3:12 pm
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I am using a Matlab code to extract Spectre transient simulation data for diode devices.  It worked when my tool versions are as follows:

mmsim 11.1.ISR20

matlab 7.11

redhat 6

But when I switched over to the following tool versions, my Matlab code no longer works:

mmsim 16.1.ISR9

matlab 8.3

readhat 6

The funny thing is, using the same Matlab code in the latter tool versions I have no problem extracting DC operating data for diode devices.  It also works for both MOSFET DC an transient device data.

Do I just need to change Matlab to another version (if so, which ones?)?  Or was there some sort of change in the diode device transient data format between mmsim 11 and mmsim 16 that my Matlab code need to adapt to?

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Sprctre simulation with no schematic cells....

May 9, 2019, 8:22 pm
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Hi Team

I want to simulate the top level of my IC with the ESD device. However, the ESD devices from the PDK are modeled without schematic views. The available views are auCdl, auLvs, hspiceD, hspiceS, layout, spectre, symbol.

Can anyone teach me how can I simulate these ESD devices in my simulation?

Thanks

MD 

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"readns" in DC Corner Simulation

May 9, 2019, 10:02 pm
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Hello,

I have some trouble with DC convergence problem. I add a state-file using "dc-->Options-->readns" and make it converge while I can see the reading procedure in the output Logs. 

But when I started a Corner Simulation, I found that simulation cannot converge and in the Output Logs there was no reading procedure. I thought it's because the Corner Simulation ignored my settings in "dc-->Options-->readns". So how to deal with this problem, I really hope someone can help me with that, -_-

I'm working with ADEXL in 6.1.5.

Thanks

Chen

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.SPF Pin Annotation Issue in Virtuoso

May 10, 2019, 3:20 am
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Hi,

I am trying to perform transistor level post layout simulation on a 'P&R'ed digital design. After P&R and timing optimizations, I import the post layout netlist (without physical only cells) to Virtuoso (Cadence IC 6.1.7) along with extracted .dspf file. I have the OA version of the reference standard cell library in Virtuoso in which all cell views have power and well contacts. However the .dspf from Innovus does not have these contacts in "instance" section, so that when the .dspf is annotated to the schematic netlist, spectre simulation stops throwing following error :

ERROR (SFE-45): `Xpipe_in_0__dxin': An instance of `DFQBRM1RA' needs at least 8 terminals (but has only 4). 

The schematic Netlist looks like below:

subckt DFQBRM1RA QB CK D RB VDD VSS VBN VBP
M0 (VSS CK N_2_M0_s VBN) n_12_llrvt l=1E-08 w=1E-07 sa=1.6E-07 \
sb=4E-07 nf=1 mis_flag=1 sd=200n as=2.4E-14 ad=3.315E-14 \
ps=6.2E-07 pd=7.6E-07 sca=45.7965 scb=0.032936 scc=0.00744915 m=1 \
mf=1
M1 (N_3_M1_d N_2_M0_s VSS VBN) n_12_llrvt l=1E-08 w=1E-07 sa=4E-07 \
sb=1.6E-07 nf=1 mis_flag=1 sd=200n as=3.315E-14 ad=2.4E-14 \
ps=7.6E-07 pd=6.2E-07 sca=45.7965 scb=0.032936 scc=0.00744915 m=1 \
mf=1

whereas .dspf : 

Xpipe_in_0__umc65_dxin pipe_in_0__umc65_dxin:CK pipe_in_0__umc65_dxin:D
+ pipe_in_0__umc65_dxin:QB pipe_in_0__umc65_dxin:RB DFQBRM1RA

Is there a workaround to bypass this in Virtuoso ? 

Thanks in advance

Anuradha

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Simulation with dspf_include

May 10, 2019, 6:51 am
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I'm trying to make a single testbench that will work with schematic or dspf simulations with ADE.  When switching from the schematic to dspf the hierarchical delimiter changes from "/" to ".".  Reading through old messages it appears that "/" is always for a schematic and "." for a netlist.  I also see that some extraction tools will create an amap file to take care of translation.  

I'm wondering if there is anyway to change the netlist delimiter to use a "/" so I can only have one testbench?  Alternatively, can an amap file be created manually?  Is the format documented anywhere?  In our case we are making sure the signal names exist in both the schematic and in the dspf so naming shouldn't be required.

I can think of some ugly was to do this with skill and/or hierarchical probes but I really don't want to have to mess with that...

Thanks

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Changing default editor within ADE

May 10, 2019, 7:04 am
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I'd like to be able to use "vim" as my default editor and viewer in ADE.  For example, when I view a netlist from a corner.  In the past I think I could just set

viewer = "/path/vim"

editor="/path/vim"

in my cdsinit. but this does't seem to work.

  Is there a different way?

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Abstraction Generation Error (IC 6.1.7)

May 13, 2019, 1:51 am
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Hi, I hope this question is more relevant to Custom IC forum. 

I am trying to generate the LEF files from a custom standard cell. Until I reach the abstraction step in the abstract standalone mode, everything works fine. But in verification stage, it throws an error stating 

*Error* (ABS-15074): Cell UT_10T_BENC11: Failed to complete the Verify step because the technology file does not have any appropriate sites defined for use in the verification design. Define a site and then try again.

The log file of the entire process is here : https://pastebin.com/e7nytQLQ

For some reason, the text fields and check-boxes in the Abstract -> Site pane are disabled and I cannot define an appropriate site for the placement ! The steps I followed are similar to the ones in documentation. What could possibly go wrong here ?

Thanks

Anuradha

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Maestro customization: Not to open schematic in tab, and two other issues

May 13, 2019, 4:58 am
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There are some issues we face with maestro and its default settings and we are wondering if those can be customized using ".cdsenv" ot ".cdsinit":

1. A maestro view sometimes remains locked after I close the session (Session->Quit). I don’t know why this happens or how to prevent it. Moreover, I don’t know how to remove this lock unless I restart Cadence. Having a maestro view locked is a problem is because it doesn’t allow me to check in this view into SOS.

2. When I start Explorer I can select that I want to open the schematic in a separate window (and not in a tab). But after a while I see that Explorer has already connected a tab with the schematic despite my instruction not to do so. For example if I add a "signal" to the outputs - maestro opens the schematic in a tab, despite it is open already in an extra window.  Is it possible to customize the default settings and change the behavior ?

3. When I have highlighted just one output expression and point to the delete symbol, other expressions (usually at the bottom of my expressions list) sometimes vanish! I’ve never seen such buggy behavior from ADE-L. This is compounded by the fact that the maestro state has already been automatically saved and so I cannot go back! Any idea why this happens and how it can be fixed ?

We are using ic6.1.8.

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Differential STB analysis in Explorer

May 14, 2019, 12:34 am
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In explorer I dont find the option of using differential STB probes. I had the option in ADE L.

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LM5022 convergence issue

May 15, 2019, 2:45 pm
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Hello community,

I designed a DC/DC Boost converter with the following characteristics:

- Vin 30-40 V

- Vou 325 V

- Iout 0.6 A

- switching frequency 200 kHz

I am stuck with a convergence issue. I have already tried to change the simulations options: increasing the max time step, GEAR metod and deleting the snubber as well.I hope someone will help me to sollve it.

Thank you in advance.

- GERARDO

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