Hi Andrew
I'm using transient simulation to draw the output wave forms of different LNAs, I know that Accurcy Defaults ( consevative, moderate and liberal ) manage the resolution of the wave form, but my question is how I can manage the number of sampels per period.
for example:
for frequency 1G Hz, I need to see wave form with 1000 samples per 1n sec.
Sincerely,
Kifah
Hi
I am going to start with my layout design. I have a big amplifier with a biasing circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic then if I have an error it will be hard to identify and or more difficult to correct it. The difficulty will rise exponentially if the correction needs to be redesigned for some parts in the middle of the layout.
Is there an option in cadence layout tools where I can run the LVS at any level of my layout design by excluding the remaining of the circuit. Just as an example I would select to layout only the differential pair transistors then I run the LVS, if LVS is ok then I continue to layout the next transistors and so on until I finish with the circuit. Such an option will be also useful to simulate the circuit at each added part of the layout.
I have tried similar kind of trick by dividing the circuit in many parts and put every part in symbol and layout it individually, after then I connect the whole symbols to build back my circuit, but this method is mostly like designing digital system from different cells. However, in digital cells are mostly unique cells where one can connect them easily, not like the analog circuit cells.
Thanks
Recently, I mainly research the achievement of digital standard cell library. For the given library cell layout, I'm planning to extrate the LEF file for floorplan and placement. But I don't know how to abstract the physical informaltion file. I learn there are two ways.
(1) At the CIW of Virtuoso, "File > Export > LEF", is this true way to get LEF for floorplan and placement?
(2) Use softeware " Abstrate Editor", but this operation is complex, could anyone help me?
I don't know which way is true? If the second way is true , I hope I can get some guide about how to operate.
I have read the article "Cadence Application Infrastructure User Guide IC6.1.7" to understand the CSF search mechanism. Whilst playing around with the settings, I found that it still loads the ".cdsinit" from $HOME, even if I explicitly did exclude/comment this location in "setup.loc".
In my workarea, the following files are used:
setup.loc: only "." is enabled as search-location, all others are commented
csfLookupConfig: only "NONE" is set
For my understanding, the above settings should result in not loading any .cdsinit. But I clearly see that the ~/.cdsinit is loaded (by printing a dedicated message into CIW). I am using ic6.1.7.500.1400.
# cdswhich -lookupconfig .cdsinit
Info (cdswhich): Cadence software is not configured to locate
file '.cdsinit' via Cadence Search File mechanism
Question1: Why does virtuoso load the ~/.cdsinit ?
Another thing I did not clearly understand from the above mentioned article, is the requirement for the "csfLookupConfig" file. According to my tests it might be enough to have "cfsLookupConfig" in my workarea to define what file to load via CSF.
Question2: Do I need to have this file in all locations defined in setup.loc, or is it enough to just have it in my workarea (which is the first search location in setup.loc) ?
Rgds.
Holger
I have a script that runs a transient analysis and it saves the nodes at the initial and final time points. For both of those time points I'm trying to run a stability analysis, but for both stability analysis runs I keep getting results for only the initial time point i.e. I can't figure out how to configure the second stability analysis run to use the "state" saved at the final time point. Some of the code in my Ocean script appears below - it contains some extraneous stuff and the analysis command for the second stability run has my latest attempt at trying to make it all work, but hopefully there's enough to highlight the issue.
resultsDir(strcat(defaultpath "/" corner_name))
analysis('dc ?saveOppoint t)
analysis('tran ?stop "250n" ?write strcat(defaultpath "/" corner_name "/az1.fc") ?writefinal strcat(defaultpath "/" corner_name "/az2.fc") )
run()
; Next do the stability analysis for the az1 loop
resultsDir(strcat(defaultpath "/" corner_name "/stb_az1"))
delete('analysis) ; delete the previously specified analyses from the queue
analysis('stb ?start "10" ?stop "100M" ?dec "10" ?probe "/stage1/ampz/I1/vinj" ?readns strcat(defaultpath "/" corner_name "/az1.fc"))
run()
; openResults(strcat(defaultpath "/" corner_name "/stb_az1/psf"))
selectResult( 'stb )
window_id = newWindow()
awvDisplayTitle( window_id strcat("az1_stb: " corner_name) ) ; labels the tab
AZ1\ Loop\ Gain\ Phase = phaseDegUnwrapped(getData("loopGain" ?result "stb"))
AZ1\ Loop\ Gain\ dB20 = db(mag(getData("loopGain" ?result "stb")))
plot( az1\ Loop\ Gain\ dB20 ?expr '( "az1 Loop Gain dB20" ) )
plot( az1\ Loop\ Gain\ Phase ?expr '( "az1 Loop Gain Phase" ) )
; Next do the stability analysis for the az2 loop
resultsDir(strcat(defaultpath "/" corner_name "/stb_az2"))
delete('analysis) ; delete the previously specified stability analyses
analysis('stb ?start "10" ?stop "100M" ?dec "10" ?probe "/stage1/ampz/I1/vinj" ?force "all" ?readforce strcat(defaultpath "/" corner_name "/az2.fc"))
run()
; openResults(strcat(defaultpath "/" corner_name "/stb_az2/psf"))
selectResult( 'stb )
AZ2\ Loop\ Gain\ Phase = phaseDegUnwrapped(getData("loopGain" ?result "stb"))
AZ2\ Loop\ Gain\ dB20 = db(mag(getData("loopGain" ?result "stb")))
plot( az2\ Loop\ Gain\ dB20 ?expr '( "az2 Loop Gain dB20" ) )
plot( az2\ Loop\ Gain\ Phase ?expr '( "az2 Loop Gain Phase" ) )
Hi,
I'm using virtuoso ICADVM18.1-64b.83 and spectre 18.1.0.077.
I have a port generating two tones, they have a power of P1 and P2 as design variables. I made those variables global variables in Meastro. I assigned a value to P1 and I set P2 equal to P1. I have a qpss analysis in which variable P1 is swept. In the simulation, only P1 is swept and P2 is constant, although I set P2 equal to P1 in the global variables. The global variables only seem to be evaluated at the start of the simulation. I want to sweep them simultaneously. I first thought of adding a second sweep for P2 in the qpss analysis, but I assume that that will be treated as an individual sweep and not that they (P1 and P2) are swept at the same time.
I prefer not to set the power parameter of the second tone equal to P1, because I would like to run another simulation in which these powers are not equal.
Creating two testbenches, one with a port with P1 for both power parameters and one testbench with a port with P1 and P2 for either power parameter is also possible. But this is not very neat, because I than have to apply a change in the testbench twice.
What would be a neat way to achieve this?
Regards,
Emiel
Hi,
I'm using virtuoso ICADVM18.1-64b.83 and spectre 18.1.0.077.
I've set the max. jobs, in the Job-setup relatively high (28).
I've set the High-Performance Simulation Options to APS and multi-threading with manual the number of threads equal to 28 as well.
The number of available tokens is not limiting.
When sweeping a design variable in Meastro (in the Data View), the number of created jobs and thread usage is as expected.
However, when instead of sweeping a design variable in the Data View, sweeping it only in the Analysis (qpss) itself, only a single job is created and a single thread is used. How can ensure/allow that a sweep in the analysis itself is parallelized as well during simulation?
When only a single tests/analysis is ran, a window with spectre.out pops up. This doesn't pop up when there are multiple tests/analysis, is there a way to still (live) see the spectre.out for a specific analysis during a simulation with multiple tests/analysis?
Regards,
Emiel
Hi,
It looks like sweeping variables can only be defined from "global variable" section (not "Design variables" from each test).
In my case, transient and stb sim have different test benches, so I put them into different tests, but with that, I can not set sweep variable exclusive to each test for above reason.
any solutions? I'd like to keep different test within the same adexl
thanks,
Kevin
Hi,
I have a case as below:
sim1: sweep code1 and based on output1 value (w. a threshold), decide which code1 to use
sim2: set code1 to be the one chosen from sim1, and sweep code2.
I've been doing this manually for a long time, and wonder if either adexl or assembler can combine and automate these two sims?
thanks,
Kevin
Hello there!
I would like to know whether (and in case how) it is possible to include into the spectre circuit netlist the .spef file, generated after the P&R, in order to simulate the circuit also with the parasitic Rs and Cs.
Thank you in advance.
Hello,
when I opened layout of "A" and launched layout XL, the schematic popped was of "B". I did update connectivity reference to schematic of "A". But, the whole hierarchy of "A" is having connectivity reference pointing to the counterparts of "B".
Please let me know how to update connectivity reference hierarchically.
Please note. A and B are similar design and both are in same library
I was looking for a way to run a transient analysis and at various times along the way perform an AC analysis. I found a way to do this via e.g.:
analysis('tran ?stop "250n" ?actimes list("0" "250n") ?acnames list("stb") )
analysis('stb ?start "10" ?stop "100M" ?dec "10" ?probe "/stage1/amp/I1/vinj" ?probe "/stage2/amp/I1/vinj" )
run()
However at the times I want to pause the transient analysis to perform the AC analysis I actually want to perform multiple AC analyses. An example reason is that my circuit is a multi-stage switched capacitor amplifier and in one phase all of the stages are disconnected so I can easily do separate stability analyses for each stage without them interfering with each other.
The method outlined in the code above only lets me do one AC analysis per paused transient time. I know there is a way to save the full transient state at various points during the transient simulation. Is there a way later to retrieve that state and force the circuit to use it for multiple subsequent AC analyses?
Is there a shortcut or something to bring ADE to front (or to make it active or something like that I don't know how it is called)? The problem is that when multiple schematics and ADEs are opened at the same times.
So it is a bit inconvenient to find the ADE of the opening schematic.
I want to bring all ADE window not just some parts like output setting, variables, etc.
In for instance the port cell in analogLib you can enter for a certain signal either the Amplitude (Vpk) or the Amplitude (dBm). When one of them gets filled in, the other field blanks out.
Is it possible to achieve the same using verilogA? If so how would this be implemented?
Regards,
Emiel
Hi,
When I am trying to do some functions in layout the below errors are coming. Can you please help me to find the problem.
To create pin:
ERROR
leHiCreateChoiceOfPin()
* Field is "manualPinMode" *
*Error* hiCreateRadioField: The initial value, "auto pin", must be contained in the choice list, ("rectangle" "dot" "polygon" "circle").
For device swaping:
lxHiSwap()
t
*Error* return: cannot return to prog in a different eval activation
*WARNING* (GE-2042): An unexpected error occurred while applying geiAppendCDFToPlForm SKILL function.
The reported error is : nil.
Thanks & Regards,
Bala
I'm tying to test my design using MATLAB. Specifically, I'm exporting time domain simulation data into MATLAB to do FFT in MATLAB.
FFT requires coherently sample data. Therefore, my time domain data needs precise time step. For instance, for a sampling frequency of 50MHz, my time step must be 20ns.
I tried setting this in ADE-> transient simulation options window. However, for some reason, the time step defaults to ~ps.
Is there anyway I can set a time step in CADENCE and expect the same timestep in the simulation data?
Hello, everyone, I need you to help me deal with the error of Abstracting LEF files.
In the process of "Abstract and Verify step" , I meet these error reminder.
********************************************************************************
Running: defout -lib Abstract_files -cell INVM0R -view abstract.ver -log defout.log -def .abstract/verify/PcsCell.def -ver 5.6
Elapsed Time: 7.8s
defout translation completed (errors: 0, warnings: 0).
INFO (ABS-15019): Starting Silicon Ensemble
*Error* (ABS-15041): Cell INVM0R: Unable to start the target place-and-route system. Check the content of the Target system commandline option, in the Verify step, and ensure that a target system license exists. Also check that the system is on your search path and then try again.
*Error* (ABS-15040): Cell INVM0R: Unable to verify abstract view in target place-and-route system. Refer to the place-and-route system's log file in .abstract/verify for more information.
INFO (ABS-11901): Cell INVM0R: Step Verify finished
INFO (ABS-11900): Cell INVM1R: Step Verify started
Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.03s.
INFO (DB-120008): oaSocket connection timeout value was set to 2 seconds.
********************************************************************************
Hello All,
When I open Layout XL I receive this message from CIW
*WARNING* dlopen: /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so: /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so: undefined symbol: _ZN7QObject13connectNotifyEPKc
*WARNING* Failed to open shared object file /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/lib/64bit/libavview.so
*WARNING* (LE-104272): Assura has not been installed in this hierarchy.
Than I check versions of Assura and IC Design Envirmont
$which assura
/eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/bin/assura
$ assura -v
Assura (R) Physical Verification Version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12
Release 4.1_USR5_HF15
Copyright (c) Cadence Design Systems. All rights reserved.
@(#)$CDS: assura_64 version av4.1:Production:dfII6.1.7-64b:IC6.1.7-64b.500.12 05/03/2018 21:53 (sjfhw625) $
sub-version 4.1_USR5_HF15, integ signature 2018-05-03-2129
run on server.adress from /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115/tools.lnx86/assura/bin/64bit/assura on Mon May 6 19:37:15 2019
No mcf file specified
***** Assura terminated abnormally *****
and when check IC design version from help menu, it is IC6.1.8-64b.83
This situation occurs after update cadence tools. Here is also part of my .cshrc file
setenv CDS_ASSURA /eda/cadence/2018-19/RHELx86/ASSURA_04.15.115
setenv ASSURAHOME $CDS_ASSURA
setenv SUBSTRATESTORMHOME $ASSURAHOME # For Assura-RF
setenv LANG C
setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/bin"
setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/assura/bin"
setenv PATH "${PATH}:${CDS_ASSURA}/tools.lnx86/dfII/bin"
setenv PATH "${PATH}:${SUBSTRATESTORMHOME}/bin"
#setenv ASSURA_AUTO_64BIT ALL
alias help_cds_assura '$CDS_ASSURA/tools/bin/cdnshelp &'
I am not sure are they relevant but I am also reviecing errors at the begining of IC
libGL error: No matching fbConfigs or visuals found
libGL error: No matching fbConfigs or visuals found
libGL error: failed to load driver: swrast
libGL error: failed to load driver: swrast
Can any one help me about
Hello,
The problem is expressed in subject: does exist some technique that allow to show all signal drivers at a particular time
Thanks in advance.
Hi all,
I have a design which uses a few design variables (e.g. the amplitude of a port). When I change the value of the variables in ADE L between simulations, this change is not detected and the design does not get renetlisted. I get the same results before and after the change. This is pretty annoying, especially for parametric analyses which doesn't work either.
What can be the reason that the renetlisting does not occur when changing a variable?
Thanks, Christoph