Hi everyone,
I am using cadence ICADV 12.3 and ADE XL for my simulations. I am trying to setup integration between cadence and Matlab to do my post simulation processing. I saw some tutorials online but I was not able to find anything to help me setup this connection and the related settings in both Matlab and cadence side.I would appreciate any sort of help in this regard.
Hi,
I am trying to do a simple RC transient simulation in Cadence virtuoso. Please see the circuit below:
I am trying to see the transient current and voltage of the capacitor being charged,however I got the following simulation result:
where /net3 is the capacitor voltage and CO/plus is the capacitor current. This looks totally incorrect, and I have my simulation configuration as:
Could anyone help me figure out the issue? Thanks!
Hi,
I am trying to go through a tutorial 'FreePDK15:Analog Artist with HSPICE' from the following link.
https://www.eda.ncsu.edu/wiki/FreePDK15:Analog_Artist_with_HSPICE#Saving_the_HSPICE_Netlist
Once I save the generated HSPICE NETLIST, as inv.sp, I get an error with the following text in CDS.log window and a dialog box opening that says 'hspice: command not found'.
Can anyone suggets me how to solve the problem? Thanks in advance
Netlisting Statistics:
Number of components: 6
Elapsed time: 1.0s (6.00/s)
Errors: 0 Warnings: 0
...successful.
compose simulator input file...
...successful.
start simulator if needed...
...successful.
*Warning* The version of the Hspice simulator that you are using may not
support the generation of PSF output on Linux. If you are having
trouble viewing simulation results, please contact Hspice customer
support to identify the version that supports this capability.
simulate...
INFO (ADE-3069): Errors encountered during simulation. For more information, see the log files
accessible from the Simulation -> Output Log menu.
Hi,
I have an verilog-A oscillator model which has a certain jitter. Using transient simulation I can get the total period jitter which matches the input jitter to the model. But I would like to have the phase noise across frequency of this model. I know I can't use PSS noise but not sure how to get it using transient simulation. Can anyone help?
Thanks
Regards,
Sherif
Hi Everyone,
Can someone point to some place with documentation about calcval: how it works, what's for, examples?
Regards
In cadence virtuoso, with scl pdk 180 nm technology, the schematic is correct and is showing the correct pre layout simulation result using ADE L. After designing the Layout, there is no DRC error found and LVS result is also correct but the post layout simulation result I am getting is wrong ... as in pre layout simulation, the output voltage is coming out to be 1.0024V and in post layout simulation, for the same set of inputs, output is coming out to be 1.63V. Please give some solution.
I'm using ICADV12.3-64b.500.21 with Calibre interactive v2018.4_25.17.
From the schematic view it is easy to perform (parameterized) sweeps of device parameters and do simulations.
I would like to do the same with the layout and an extraction simulation (using Calibre xACT).
The layout is already suitable, such that when the parameters are changed, the connecting wires and pins are still correct.
Any advice on how to get this done would be nice.
The first problem is that the layout does not accept variables. Should I generate a bunch of layouts with the different parameter values to over come this? Is there a way such that I don't have to generate them all manually?
And once that is tackled, is there a way to simulate the whole set of generated extraction cell views in one go?
Thank you,
Emiel
Hello,
I have the following problem: My transient simulation crashes with this error message in the simulation output log:
Internal error found in spectre during transient analysis `tran'.
Encountered a critical error during simulation. Please run `mmsimpack' to pack the test case (use mmsimpack -h option to get detailed usage), and submit the case via Cadence Online Support, including the package tar file and any other information that can help identify the problem.
FATAL (CMI-2010): Assertion failed in file `MultirateMngr.cc' at line 4176.
FATAL (SPECTRE-21): Assertion failed.
Version 18.1.0.314.isr5 64bit -- 26 Mar 2019
****ASSERTION STACK****
0x4f01bde
0x5ecece
0x7fd45452d280
0x7fd45452d207
0x7fd45452e8f8
0x1743473
0x1744cae
0x12ebdd0
0x12f67b7
0x128638b
0x1063a06
0x123dcce
0x125f7ea
0x10ab09b
0x10b05e8
0x10b156c
0x3637056
0x4cd565e
0x7fd44ae7a9a4
0x44b59f3
0x44b653b
0x44af4ba
0x44ac8b1
0x44acfa7
0x7fd44ae79a22
0x4cd77d3
0x515f3f
0x516f67
0x517e62
0x4a9c59
0x7fd4545193d5
0x503075
****LIBRARIES****
/software/cadence/SPECTRE/181/tools/spectre/bin/64bit/spectre [0x400000]
/lib64/libc.so.6 [0x7fd4544f7000]
dfII/../lib/64bit/simiADEPlugin.so [0x7fd44ae76000]
I am using cadence Virtuoso 6.1.7 ISR23 and SPECTRE18.1 ISR5. The fault occurs under following conditions:
I do a transient simulation in Assembler with APS activated, limited to one thread. I sweep across a global variable (a resistor from analogLib). All simulations are done on the same computer, one after the other, no parallel jobs. The first 2 simulations of the sweep are running without any problems. The third simulation and all following will abort.
If I turn off APS, the simulation does not crash. What I also recognised: In my testbench I simulate a cellview (schematic) in which I use another cellview (operational amplifier) 2 times. If I use two different cellviews (exact same operational amplifier, just copied to a different cellview name), the simulation works fine for all runs.
Regards,
Michael
Hi,
I try expression below. It could not work.
dnl(abs(dac_out_DC) 0.625m ?mode "auto" ?crossType "rising" ?delay 0.0 ?method "end" ?units "lsb" ?nbsamples (256/VAR("dac_step")))
but it works when I use dnl(abs(dac_out_DC) 0.625m ?mode "auto" ?crossType "rising" ?delay 0.0 ?method "end" ?units "lsb" ?nbsamples 256).
The difference between these two expression is the "bnsamples" argument. Do you know why?
Thanks
Hi Andrew!
I was checking for information regarding instance parameters for my study purpose. In the psf file, there are many files with extension ".info". These .info files are binary. Is there any way to open those files?
Hi all!
I'm having difficulties to find the desirable OP point during a DC sweep with a comparator that use a amux a resistor string to generate the hysteresis. The simulator find most of the time a VDD/2 stable operation point.
I'm defining nodeset statements, which are only valid to the OP point calculation but as DC sweeps the input, it makes the output to trigger and the nodeset statement is not longer valid.
Does the nodeset statement consider only for OP? Or it is also considered for each step of DC sweep?
Can I define a nodeset dependent on a parameter condition (ternary operator), something like (vn_par>vref_par)?0:avdd_par
Thanks!
With reference to this post:
It seems like the GUI of the new ADE Explorer tool does not allow lists (eg.: [1.1 2.0 3]) to be passed to the Spectre netlist as a parameter containing a list of values.
I get an invalid expression error message from the GUI when I try to input the list to an ADE Explorer variable. It the asks me to specify the parameter using double quotes. When I do this however, the Spectre netlist initializes the Spectre parameter to a string (eg.: myparam="[1.1 2 0.3]"). I then get a spectre error message: "A vector is expected as the value for parameter 'myparam'".
I have tried playing around with variants using commas, a single quote at the start, curly bracktes etc, but have not been able to get it running.
Is there an updated way to pass parameter arrays to VerilogA modules from variables declared in the new ADE Explorer GUI?
Hello,
I am simulating a readout chain with the harmonic balance in PSS analysis. I receive so many warning on imelt and Vgs voltages of transistors but when I see the time-domain signal, there is no such thing. Also, the circuit is very simple (an inverter with the output connected to NMOS, PMOS, or T-Gate switches) and all voltages are withing the range of 0-VDD. I think there is no way I see such crazy voltages (like 6*VDD for the Vgs) but since the warnings are very critical I became obsessed about it. I am using the version IC617. Let me know if you need further information.
PM. The THD results look good.
Hi,
I am trying to simulate a basic inverter circuit using spectre. I have generated a netlist file. when I run it, I am getting the following error
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 2: Unexpected end of line. Expected equals sign, numeric value or string value.
For your referrence, I am posting the files 'cds.lib', 'input.scs' and 'spectre.out' here. Can someone help me out. Thanks in advance
*************cds.lib********************
#Following defined by Chandrasekhar DVS
DEFINE analogLib /usr/local/IC614/tools/dfII/etc/cdslib/artist/analogLib
DEFINE US_8ths /usr/local/IC614/tools/dfII/etc/cdslib/sheets/US_8ths
DEFINE basic /usr/local/IC614/tools/dfII/etc/cdslib/basic
DEFINE cdsDefTechLib /usr/local/IC614/tools/dfII/etc/cdsDefTechLib
DEFINE NCSU_TechLib_FreePDK15 $PDK_DIR/cdslib/NCSU_TechLib_FreePDK15
DEFINE ADETutorial /home/eslam/ADETutorial_1/ADETutorial
DEFINE SPECTRE_TUTORIAL /home/eslam/ADETutorial_1/SPECTRE_TUTORIAL
#DEFINE analogLib $CDS/IC/tools/dfII/etc/cdslib/artist/analogLib
#DEFINE US_8ths $CDS/IC/tools/dfII/etc/cdslib/sheets/US_8ths
#DEFINE basic $CDS/IC/tools/dfII/etc/cdslib/basic
#DEFINE cdsDefTechLib $CDS/IC/tools/dfII/etc/cdsDefTechLib
*****************************************
************* input.scs****************
// Generated for: spectre
// Generated on: Apr 21 11:31:37 2019
// Design library name: SPECTRE_TUTORIAL
// Design cell name: myInverterTB
// Design view name: schematic
simulator lang=spectre
global 0 vdd!
parameters VDD_VAL=0.8
include "/home/eslam/ADETutorial_1/cds.lib"
// Library name: SPECTRE_TUTORIAL
// Cell name: myInverter
// View name: schematic
subckt myInverter I O inh_bulk_n inh_bulk_p
I2 (O I inh_bulk_p inh_bulk_p) pmos
I6 (O I inh_bulk_n inh_bulk_n) nmos
ends myInverter
// End of subcircuit definition.
// Library name: SPECTRE_TUTORIAL
// Cell name: myInverterTB
// View name: schematic
I5 (IN OUT 0 vdd!) myInverter
V0 (vdd! 0) vsource dc=VDD_VAL type=dc
V1 (IN 0) vsource type=pulse val0=0 val1=VDD_VAL period=20p delay=0 \
rise=1p fall=1p width=9p
C0 (OUT 0) capacitor c=1f
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=40p write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save IN OUT
saveOptions options save=allpub
**********************************************************
***************spectre.out************
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 7.1.1.187.isr11 32bit -- 18 Aug 2009
Copyright (C) 1989-2009 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
Protected by U.S. Patents:
5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238;
6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964;
6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839;
6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782;
7,085,700; 7,143,021; 7,493,240.
Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.
User: root Host: localhost.localdomain HostID: 7F0100 PID: 5290
Memory available: 1.0215 GB physical: 1.9854 GB
CPU(1 of 2): CPU 0 Intel(R) Core(TM)2 Duo CPU T6600 @ 2.20GHz 2200.000MHz
Simulating `input.scs' on localhost.localdomain at 11:40:05 AM, Sun Apr 21, 2019 (process id: 5290).
Environment variable:
SPECTRE_DEFAULTS=-E
Command line:
/usr/local/IC614/MMSIM/tools.lnx86/spectre/bin/32bit/spectre \
input.scs +escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre0_3079_6 -format sst2 -raw ../psf +lqtimeout \
900 -maxw 5 -maxn 5
spectre pid = 5290
Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /usr/local/IC614/MMSIM/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Error found by spectre during circuit read-in.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 2: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 3: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 4: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 5: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 6: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 7: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 8: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 9: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 10: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 11: Unexpected end of line. Expected equals sign, numeric value or string value.
ERROR (SFE-874): "/home/eslam/ADETutorial_1/cds.lib" 13: Unexpected end of file. Expected equals sign, numeric value or string value.
Time for parsing: CPU = 195.97 ms, elapsed = 347.244 ms.
Time accumulated: CPU = 243.962 ms, elapsed = 348.989 ms.
Peak virtual memory used = 552 Mbytes.
Aggregate audit (11:40:06 AM, Sun Apr 21, 2019):
Time used: CPU = 245 ms, elapsed = 350 ms, util. = 69.9%.
Time spent in licensing: elapsed = 177 ms, percentage of total = 50.5%.
Virtual memory used = 552 Mbytes.
spectre completes with 11 errors, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.
*********************************************************
I have written a VerilogA testbench that runs a few automated tests using IC6.1.7 and SPECTRE171.
I thought it would be useful to plot the current test phase as a string on the waveform as this could help with analog debugging along the x-axis (time).
I might have managed to update a string variable at the start of every phase, but now it seems that I cannot access the variable in the VIVA results browser. I have also changed the output format to SST2 and tried using Simvision but this also did not work. I have made sure that "saveahdlvars" is set, and I can currently access and plot all the real and integer VerilogA variables.
I have done something similar inside a SystemVerilog bench through a Mixed-Mode simulation, but right now I want to avoid expanding my bench this far.
Is there a way for me to plot this variable on a waveform viewer?
I have two circuits A and B. I simulated the circuit A and has some waveform results. Can I save those some of the waveform and use it as a input signals to simulate in the circuit B?
Hi All,
I have a top level schematic name cell_top. In cell_top I have 2 instance name cell_A and cell_B. Cell_A and cell_B are generated by innovus play and route flow which don't have any power pin. Inside of cell_A and cell_B the power net name is vdd! and vss! which inherit from vendor lib. On the cell_top, cell_A power connect to vddl_lvt and vssd_lvt and cell_B connect to vddl_mvt and vssd_mvt.
Layout is connected properly but schematic can't since there is no power pin to cell_A and cell_B. I heard that we can connect it using netSet but I don't know how to to that . Can someone please help
thanks
Nhumai
Hi everyone,
I have a circuit with couple of subcircuits inside it. I was wondering if there is a way to have a print of operation region for all transistors inside all subcircuits to make sure that all transistors are in saturation. I don't want annotation of them on the schematic since I have to go inside them individually to check for it. I would appreciate any sort of help in this regard.
Thanks,
Ata
Hello,
I'd like to obtain values of noise contributions in the circuit for each Monte Carlo run.
I was able to make Spectre output total noise for each Monte Carlo iteration into a file, but no luck with noise contributions.
Below is a made-up example: two resistors in series and I am simulating voltage noise at the point where the resistors meet. Obviously, both resistors contribute to noise. The example shows how to dump the total noise at each Monte Carlo iteration into a file called "scalars". Is there a way to make Spectre output noise contributions from r1 and r2 into the same file?
Thanks!
test.scs:
====================================================
r1 (1 0) res_model l=10e-6 w=2e-6
r2 (2 1) res_model l=15e-6 w=2e-6
vr (2 0) vsource dc=1.0 mag=1
model res_model resistor rsh=100 kf=1e-20*exp(dkf)
parameters dkf=0
statistics {
process {
vary dkf dist=gauss std=0.5
}
}
noi (1 0) noise freq=1
====================================================
test.mdl:
====================================================
alias measurement noi_test {
run noi;
export real noi_total=noi_test:out;
}
run montecarlo(numruns=10,variations='all,scalarfile="scalars") {
run noi_test;
}
====================================================
Launch command: spectre =mdl test.mdl test.scs
Spectre version: 17.1.0.238.isr4
Hi everyone,
Could someone provide some insight how to define a global/design variable in ADE Assembler Maestro in terms of an IF statement, but instead of passing just one value after evaluating the IF condition, it provides a vector (which would result in a parametric simulation)?
Example:
If Var2 == Value1, then Var1 takes the value set [Value-A Value-B Value-C] --> three simulations
If Var2 == Value2, then Var1 takes the value set [Value-D Value-D] --> two simulations
So far I can only make it work for the case when the value set has just one value (typical IF-ELSE). How is the proper syntax to achieve this? Is there a special function for this case?
Thanks!