Hello
Im currently trying to measure the delta of the further most separated waveforms obtained by corner simulation.
I have tried changing "eval type" to corners and using the peakToPeak and average functions but they seem to give me different results (peakToPeak returns Ymax-Ymin) but i Need the "offset" so to speak.
What i need is an expression that calculates dY over corners.
Is there a simple way to do this?
Hi all, Is there any bindkey to set bindkey to activate PVS-DRC/LVS windows ?
Thanks!
Using Harmonic Balance with SpectreRF in ADE Explorer, is it possible to run load-pull simulations in parallel?
By default each iteration runs sequentially regardless of the jobs setup in ADE Explorer.
Hi,
How can I report all the glitches to the gate node of a transistor?
Both below statements does not seem to work
dyn_glitch1 dyn_glitch node=[I0.IGCNTL.ICLK.I74.I69.MN.G] ] duration=20p high=0.9
dyn_glitch2 dyn_glitch node=[I0.IGCNTL.ICLK.I74.I69.A1] ] duration=20p high=0.9 //A1 is the input pin for the instance where transistor MN gate is connected
Satendra
The following products are paid for:
#INSTALLSCAPE PRODUCT "PALT812" "PALT812: Liberate AMS Client"
#INSTALLSCAPE PRODUCT "PALT810" "PALT810: Liberate AMS Server"
#INSTALLSCAPE PRODUCT "PALT411" "PALT411: Liberate MX Client"
#INSTALLSCAPE PRODUCT "PALT410" "PALT410: Liberate MX Server"
#INSTALLSCAPE PRODUCT "PALT211" "PALT211: Liberate Variety Client"
#INSTALLSCAPE PRODUCT "PALT210" "PALT210: Liberate Variety Server"
#INSTALLSCAPE PRODUCT "P95310" "P95310: Virtuoso(R) Layout Suite XL"
#INSTALLSCAPE PRODUCT "P90005" "P90005: Spectre Multi-Mode Simulation with AMS"
#INSTALLSCAPE PRODUCT "P95210" "P95210: Virtuoso(R) Analog Design Environment XL"
#INSTALLSCAPE PRODUCT "P95115" "P95115: Virtuoso(R) Schematic Editor XL"
#INSTALLSCAPE SOURCE "is/LIBERATE191/lnx86/Base"
"Base LIBERATE191 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12 LIBERATE19.1.0 Release"
"Version Base LIBERATE191 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12 LIBERATE19.1.0 Release"
#INSTALLSCAPE SOURCE "is/IC618/lnx86/Base"
"Base IC618 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12 IC6.1.8.83 Release"
"Version Base IC618 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12 IC6.1.8.83 Release"
#INSTALLSCAPE SOURCE "is/SPECTRE181/lnx86/Base" "Base SPECTRE181 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12;Ubuntu 14 18.10.077 Release"
"Version Base SPECTRE181 LINUX RHEL 6;RHEL 7;SLES 11;SLES 12;Ubuntu 14 18.10.077 Release"
All the necessary information in the key file entered.
I launch the license server
/SOFTWARE/cadence617/LIBERATE171/tools/bin/lmgrd -c /SOFTWARE/licenses/srv-work3.ti/license.dat -l /var/log/cadence/libarate.log
Error in the log file
12:10:52 (lmgrd) FlexNet Licensing (v11.13.1.3 build 176483 i86_lsb) started on srv-work3.ti (linux) (2/28/2019)
12:10:52 (lmgrd) Copyright (c) 1988-2015 Flexera Software LLC. All Rights Reserved.
12:10:52 (lmgrd) World Wide Web: http://www.flexerasoftware.com
12:10:52 (lmgrd) License file(s): /SOFTWARE/licenses/srv-work3.ti/license.dat
12:10:52 (lmgrd) lmgrd tcp-port 5280
12:10:52 (lmgrd) (@lmgrd-SLOG@) ===============================================
12:10:52 (lmgrd) (@lmgrd-SLOG@) === LMGRD ===
12:10:52 (lmgrd) (@lmgrd-SLOG@) Start-Date: Thu Feb 28 2019 12:10:52 MSK
12:10:52 (lmgrd) (@lmgrd-SLOG@) PID: 20107
12:10:52 (lmgrd) (@lmgrd-SLOG@) LMGRD Version: v11.13.1.3 build 176483 i86_lsb ( build 176483 (ipv6))
12:10:52 (lmgrd) (@lmgrd-SLOG@)
12:10:52 (lmgrd) (@lmgrd-SLOG@) === Network Info ===
12:10:52 (lmgrd) (@lmgrd-SLOG@) Listening port: 5280
12:10:52 (lmgrd) (@lmgrd-SLOG@)
12:10:52 (lmgrd) (@lmgrd-SLOG@) === Startup Info ===
12:10:52 (lmgrd) (@lmgrd-SLOG@) Server Configuration: Single Server
12:10:52 (lmgrd) (@lmgrd-SLOG@) Command-line options used at LS startup: -c /SOFTWARE/licenses/srv-work3.ti/license.dat -l /var/log/cadence/libarate.log
12:10:52 (lmgrd) (@lmgrd-SLOG@) License file(s) used: /SOFTWARE/licenses/srv-work3.ti/license.dat
12:10:52 (lmgrd) (@lmgrd-SLOG@) ===============================================
12:10:52 (lmgrd) Starting vendor daemons ...
12:10:52 (lmgrd) Started cdslmd (internet tcp_port 35601 pid 24235)
12:10:52 (cdslmd) FlexNet Licensing version v11.13.1.3 build 176483 i86_lsb
CADENCE_INFO_MSG: Cadence kit version: 12.07-p001
12:10:52 (cdslmd) SLOG: Summary LOG statistics is enabled.
12:10:52 (cdslmd) SLOG: FNPLS-INTERNAL-CKPT1
12:10:53 (cdslmd) SLOG: VM Status: 0
12:10:53 (cdslmd) SLOG: FNPLS-INTERNAL-CKPT2
12:10:53 (cdslmd) License server system started on srv-work3.ti
12:10:53 (cdslmd) No features to serve, exiting
12:10:53 (cdslmd) EXITING DUE TO SIGNAL 36 Exit reason 4
12:10:53 (lmgrd) cdslmd exited with status 36 (No features to serve)
12:10:53 (lmgrd) cdslmd daemon found no features. Please correct
12:10:53 (lmgrd) license file and re-start daemons.
12:10:53 (lmgrd)
12:10:53 (lmgrd) This may be due to the fact that you are using
12:10:53 (lmgrd) a different license file from the one you expect.
12:10:53 (lmgrd) Check to make sure that:
12:10:53 (lmgrd) /SOFTWARE/licenses/srv-work3.ti/license.dat
12:10:53 (lmgrd) is the license file you want to use.
12:10:53 (lmgrd)
12:11:35 (lmgrd) -----------------------------------------------
12:11:35 (lmgrd) Please Note:
12:11:35 (lmgrd)
12:11:35 (lmgrd) This log is intended for debug purposes only.
12:11:35 (lmgrd) In order to capture accurate license
12:11:35 (lmgrd) usage data into an organized repository,
12:11:35 (lmgrd) please enable report logging. Use Flexera Software LLC's
12:11:35 (lmgrd) software license administration solution,
12:11:35 (lmgrd) FlexNet Manager, to readily gain visibility
12:11:35 (lmgrd) into license usage data and to create
12:11:35 (lmgrd) insightful reports on critical information like
12:11:35 (lmgrd) license availability and usage. FlexNet Manager
12:11:35 (lmgrd) can be fully automated to run these reports on
12:11:35 (lmgrd) schedule and can be used to track license
12:11:35 (lmgrd) servers and usage across a heterogeneous
12:11:35 (lmgrd) network of servers including Windows NT, Linux
12:11:35 (lmgrd) and UNIX. Contact Flexera Software LLC at
12:11:35 (lmgrd) www.flexerasoftware.com for more details on how to
12:11:35 (lmgrd) obtain an evaluation copy of FlexNet Manager
12:11:35 (lmgrd) for your enterprise.
12:11:35 (lmgrd)
Help fix the error
Hi all!
I want to clip a waveform which was generated by a reverse DC analysis. Unfortunately I have found that clip function doesn't work with reversed DC waveforms.
Is there some workaround ? I have tried a composition of functions including flip without sucess.
Thanks!
there is a check box for dc simulation, no question for that part.
I tried to put "homotopy=dptran" in the ac simulation->option->additionalparameters, but the ac simulation still tired "gmin" and "source" method before dptran.
I searched online but didn't find any useful information, I also tried "set homotopy=dptran", it causes a simulator error.
What's the correct syntax?
Regards
hello experts,
I suppose there should be some command/tool to list the computation heavy cell/circuit so designers can swap with faster behavioral models? how can I do that?
IC617 + Spectre 16.1
thanks,
David
Hi,
I am designing a new PDK/Tech file. Tech file is uploaded in CIW and layers looks fine in Layout suite. But when I open Layout from Schematic or generate from source, I cannot see any layout instances except gnd and vdd. The following warnings
Layout instances and terminals do not match the source
Cannot create a layout instance from schematic instance M0 because there is no layout master defined.
Can someone please help me?
Kind Regards,
Waqas
Hello,
The log content:
\o ERROR (OSSHNL-153): Failed to initialize incremental netlisting because the run directory contains
\o netlist data from the previous netlisting session which has a corrupt global
\o map structure file '/xxx/maestro/results/maestro/Interactive/1/xxx/netlist/ihnl/globalmap'. Remove the "ihnl" and "map" directories from the
\o current run directory and netlist again.
\o
\o "ERROR (OSSHNL-512): Failed to generate netlist because incremental netlisting data from the previous session is corrupt or missing. Clean the run directory and netlist the entire design.\n"
\o End netlisting Mar 6 12:02:05 2019
\o ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
\o ...unsuccessful.
Failure description:
Maestro is mapped from adexl by "open with". Test_A is defined by config. Simulation using adexl is fine.
When run sim with Maestro (assembler), such incremental netlist problem happen.
When define Test_A by schematic, no problem.
I try to re-start cadence, remove history, not fix.
Anyone has clue ?
BR
Hello,
If Ihave 'fsdb' file which represents the simulations results of a simulation (waveforms), is there a way to transform it into pwl (piece wise linear) signals that I can use as stimulis ?
Thanks,
Kotb
Hi,
I need to run MC simulation, say 100 runs, and for every single run of these 100 I want to keep saving a voltage to a text file, for ex. at the system clock and I want to do this as the simulation is running. It would be convenient to keep all files in the same directory of my choice, and not in the respective MC run directories. I know how to do the file saving part. What I can't figure out is how to name the files such that they don't over-write each other. Is there anything specific to the individual MC runs that I can include in the file name and how can I access that specific information from the simulation? For example, if I can include the MC run number it would solve the problem. Or maybe something else that distinguishes one MC run from another.
Thanks in advance.
Hi All,
I am trying to run Calibre Quantus QRC,
First I make a QRC command file name "tech.def".
Here is my code:
DEFINE pex_tech /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_FuncCmax_Detailed
process_technology
-technology_library_file /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/tech.def
-technology_name pex_tech
-ruleset_name /home/marben/Desktop/Components/Calibre/PARASITIC/CMOS55LPE_5_00_01_00_LB/CMOS55LPE_5_00_01_00_LB_Nominal_Copied_Detailed/lvsfile
But I have an error in CIW like this:
*WARNING* The number of errors was detected in Extract Tab: 1
I also got an error in CIW like this.
Please help me.
Best regards,
Marben
Dear friends,
It is the first time for me to design a fully differential amplifier and I don't know know most of the simulation setup,
I would like to ask you please to guide me for this simulations,
I would like to first ask you how to simulate the DC gain, GBW and Phase margin.
I heard that there is a Balun source in cadence which convert the single ended input to fully differential to provide the inputs of the amplifier with equal and out of phase signals.
Also I heard about stability simulation is better to extract these parameters using diffstbprobe.
I am looking forward for your help
Best Regards
I am trying to design an analog li-ion charging IC as my academic project. Is there any simple equivalent Circuit Model of Li-ion cell which I can use in virtuoso ADL simulation for transient response simulation of charging circuit?
Hi everyone.
I am trying to get the transistor shapes (i.e. rectangles) of my devices after running PVS LVS. What I can find in the generated output netlist are the X and Y coordinates. However, is there also a way to get the full bounding box including the correct rotation?
Thanks for your help
Christoph
Has anyone seen this before? How to get rid of this?
Thanks in advance!
Hello,
I am a newbie to this forum so excuse me for mt first question.
I am getting some strange error without any explanation while performing "check and save" for my schematic on virtuoso.
Error reads:
*Error* round: argument #1 should be a number (type template = "n") - nil
Version: ICADV12.3-64b.500.21
Can someone share the reason for this and possible fix to try out?
Thank you!
Harsh
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Hi! How can I increase the maximum distance for capacitance extraction in Quantus?
In a simple testbench I put two 100um-long metal traces (M8), and if they are 1um apart Quantus extracts the coupling capacitor (~3.3fF), but if they are 2um apart there is no coupling capacitor anymore (while a third-party extraction tool gives ~2fF of coupling for this case).
I tried the "Extend Checking Distance" option mentioned in the manual, but it had no effect.
Thanks and regards,
Jorge.
P.S. I am using the "C only" extraction type with "Coupled" cap coupling mode. My MinC filtering thresholds are set to 0.001fF and 0.01%. Quantus 18.2.1-s210 on TSMC 16nm PDK