Hi all.
I'm sweeping the linear regulator input voltage on DC from 0V to maximum expected Vin. However, as the OTA that makes part of LDO is internally supplied by the output voltage, the simulation will never turn on the OTA and it will find a very stable point of operation in 0V. it is like the dilemma of chicken and egg.
How I could force to start the OTA and calculate the minimim input voltage?
Thanks
Dear All,
I am designing robust SRAM memory cells for space application. I have to calculate the minimum critical charge that each memory node can tolerate until data flips.
I run ADE L several times (let’s say around 300-400 times) to find the minimum critical charge and optimum transistors sizes. Each time, I opened up the waveform viewer to check the waveforms. When I found the optimum sizes, I wrote down them and turned off my laptop. The day after that, when I again run ADE L, my saved results were not the optimum! Again, I had to run the simulator several times to find the optimum transistor sizes; they were close to the previous data, but different numbers! I am sure I did not make any mistakes. What can be the problem? Is it a bug?
Bests,
Hello.
I would like to use the "eventtime" variable in the calculator to perform a certain computation.
The "eventtime" variable I am talking about is the PAC sampling time, calculated when a certain condition is met. (In my case the condition is when a given net reaches vdd/2. This can be set-up in the PAC analysis form).
I can explicit access the computed value of "eventtime" in the Direct Plot-> PAC -> Variable Value (eventtime). In my case it's something like 4.50996n
However, as this value may change for different testing conditions, I would like to get it via variable evaluation. Something like: VAR("eventtime"), so I can use it in my calculator.
This what I currently have in the calculator:
value((v("/vop" ?result "pac-pac_cross") - v("/von" ?result "pac-pac_cross")) '"eventtime" '4.50996e-09)
This is what I would like to use instead.
value((v("/vop" ?result "pac-pac_cross") - v("/von" ?result "pac-pac_cross")) '"eventtime" VAR("eventtime"))
The latter expression is of course not working because VAR("eventtime") is not a correct expression.
The setup I am working with is: Virtuoso 6.1.7-64b and Spectre 18.1.0.169.isr2 64bit
Thank you for any help.
GR
Looking to generate a flat hspiceD or spectre netlist to feed some netlist checking scripts. Flat netlists are much easier to post process with simple scripts. Netlist size not an issue.
Currently using ocn replay from this forum:
envSetVal("asimenv.startup" "projectDir" 'string "testnetlist_dir")
simulator('hspiceD)
design("test" "D2L_X_COUPLE" "schematic")
createNetlist()
What can I add to get a flat netlist instead of hierarchical ?
I did try to export flat cdl from ciw, but that netlister renames all the nets and instances.
Can't seem to get si to create hspiceD in batch mode either.
Thanks for any guidance you can provide
Hi there,
Some experience with spectre transient simulatin and multithreding?
I've just made some tests , mmsim 15.1.0, but I don't see big difference between 1xcpu and 4xcpu on machines with identical CPUs:
1xCPU: Time used: CPU = 10.2 ks (2h 49m 49s), elapsed = 10.2 ks (2h 50m 21s), util. = 99.7%.
4xCPU: Time used: CPU = 9.96 ks (2h 45m 59s), elapsed = 9.98 ks (2h 46m 25s), util. = 99.7%.
Why I'm asking this: right now the simulation is started via a ocean script,hostMode(local) because I what to have the simulation running in blocking mode , I need to know when it finished to trigger some post processing script.
I have a request to add the possibility to set number of CPUs. I want to know if the effort makes sense.
My understating is that I cannot specify numbers of cpus in local mode , s I have to go in distributed mode, and in our environment I have to use ?drmsCmd mechanism.
The drmsCmd is nonblocking and it means that I have to implement also a monitoring process to know when the simulation ends.
Further more with the 'local' mode I have full control on where to create the psf directory passing to the ocean script the ResultsDir as argument I will have the sim results in : ResultsDir"/psf" , with distributed I have to take care also about the possible job renaming.
Important: there is just one transient simulation.
Thank you,
Marcel
Hi all!
Could you pls. help me to resolve some issue.
When I start Assura QRC form layout view - all works fine, but when I try to start the same in the batch mode, I have following error:
SAVEDIR=`beginFlattenInputs`
beginFlattenInputs
export SAVEDIR
/bin/mv -f NET h_NET
flatnet -V -li -h '/' h_NET NET
Usage so far 0.00 user, 0.00 sys, 0.00 elapsed, 100284.0 kbytes
run out of memory or swap space for malloc(): Cannot allocate memory
ERROR (LBMISC-215023): run out of memory or swap space for malloc(): 0 bytes asked
ERROR (LBRCXM-609): Bad return status from RCX run. 0xff00
INFO (LBRCXM-709): ***** Quantus QRC terminated abnormally *****
Virtuoso version is: sub-version IC6.1.7-64b.500.7
QRC version is: 14.2.2-s209
Hi,
I am using AMS to do simulations( virtuoso 6.1.7-64b) , however, I'm used to adopting Waveview as waveform viewer.
Because Waveview doesn't support the psf format of spectre, I need to change the output format to "psfbin".
And I follow the flow:
1. Setting "config" view.
2. Enter envSetVal("spectre.outputs" "simOutputFormat" 'string "psfbin") to CIW.
3. Launch ADE L, and finish the setting of library, connect rules, APS.
4. Select OSS-based netlister with irun, and Create netlist
5. Press "Simulation and Run" of ADE
However, there seems no pdfbin file in the output folder.
Is there anything wrong in my settings?
Thank you.
Hello,
I am using Virtuoso version IC6.1.7.
I would like to implement the following functions of the calculator in an MDL file:
- rshift (or any type of time shift)
- settlingTime
- firstVal
- xval
- xmin
- ymin
How can I do that?
Moreover, I would like to use the variables that I define in ADE L in the expressions inside MDL file. How can I do that?
Many thanks in advance.
Best regards,
Can
Hi! I noticed in the TRAN simulation of a 4GHz clock buffer that the calculated jitter at the output differs slightly depending on which outputs are saved. If I choose to save nothing but the output clock, I get ~17fs; if I save also a drain current of one of the devices in a diff pair in the DUT, I get ~18fs, and saving the currents of both devices gives ~19fs.
I double-checked the netlists produced in all cases, and indeed the only differences are the "save" statements.
What could be causing this? Reducing the maxstep from 1ps to 0.1ps seems to solve the problem, but I was expecting that for a given maxstep the results should be consistent irrespective to the outputs saved, shouldn't them?
I'm using Spectre 17.1.0.307.isr6 64b
Thanks and regards, Jorge.
Hello,
I am using Virtuoso version IC6.1.7.
I would like to termiante a transient simulation on an event using autostop with MDL option. My circuit is a 5-stage static inverter ring oscillator. I provide a ramp on vdd and modulate the output frequency at node vout. The frequency rises from ~1GHz to ~2GHz during the transient simulation and I can observe this using the calculator function freq. In my MDL file, create an event which is triggered when the frequency crosses 1.5GHz:
alias measurement tran_autostop {
export real Tcross
run tran
Tcross = cross( sig=freq(sig=V(vout), thresh=0.5, dir='rise), dir='rise, n=1, thresh=1500000000.0 )
}
run tran_autostop
However, the simulation does not stop. What do I need to do to have the simulation stopped when this event (frequency's crossing a threshold) is triggered?
Many thanks in advance.
Best regards,
Can
Hi,
I have something like this in my veriloga
for(i=in_sig_cnt-1;i>=0;i=i-1) begin
//rise time for sig
@(cross(V(sig[i])-(ref_vdd/2), +1)) begin
if(write_flag&&((maxtime-mintime)<=10e-9)) begin
$fwrite(fpt, "\n%s %d @t=%Es %s %s ", tag,in_sig_cnt,$abstime, ratio,signal_name);
for(j=in_sig_cnt-1;j>=0;j=j-1) begin
$fwrite(fpt, "%d;%e;",sigd[j],sigt[j]);
end
end
end
I see that in the report file, the two fwrite gets overlapped. Is there a way to print first fwrite then next fwrite (with j for loop).
Satendra
I am getting this warning for all the libraries in virtuoso (IC616)
Warning: ddiAddLibtoOA: Can't access library'Library name" at path "path" in OA 2.2. OA Exception is: Syntax error in .oalib file of the library.
and can't access cells in user defined libraries also.
Even newly created libraries also show this warning and my design under the library disappear after some time
Hello everyone,
I would like to run simulations just like in these 2 graphics but I dont know how to run it. In my project I have 4 v-bit sources as digital input that provides bit patterns, I also have AC input to run AC analysis. How can I run these simulations ? Which simulation type and how would provide me these graphics. I would like to see result exactly like in these graphics. 
Second question is how can I plot the graphic by using differential inputs ? Just like the graphic I provided below, I woud like to plot I2-I1 versus V2-V1. I am really confused what to sweep and how to sweep while bits are changing.
I have already checked forums but could not find helpful solution. Any help or tip would be appreciated. I use Cadence 6.1.6 and ADE L. Thank you
The input signal for the simulation that I'm running comes from a .csv file that I generated in matlab. When I generate the file in matlab, the signal looks smooth and has a high resolution. However, when I run the simulation in ADE L, it appears that my smooth signal is automatically sampled at a rate that is far too course for my needs. I'm trying to keep the area under that signal as precise as I can and it looks like the sampling that is happening when I run the simulation is having some unintended effects on the output. Is there anyway I can get around this? I'd like to have the input file unaltered before it is used in the simulation.
I am trying to simulate the config view of a testbench but it is failing at the netlisting step. I am getting the following error in my CIW
"ERROR (OSSHNL-512): Failed to generate netlist because incremental netlisting data from the previous session is corrupt or missing. Clean the run directory and netlist the entire design.\n"
The top cell view of my config view is the schematic version of the testbench.
I have no issues when I click I run netlist and run by choosing the design to be the schematic view in ADE Explorer.
Where is the run directory located?
Hello,
I just updated to Cadence Virtuoso IC6.1.8-CAT 37 and when I delete both design variables and global variables from both the schematic and test bench setup in the data view assistance in ADE XL, the deleted variables show up when I open the same schematic from which the design variables were deleted.
How can I fix this?
While using Cadence version 5.1.0, everything in the schematic window shows up yellow (as shown in picture below). The cadence version I am using is icfb 5.1.0. I am using x2goclient to remotely log in to the server. I tried replacing the "display.drf" file and it is still the same. 
Does anyone have a clue why?
Hi,
When I open the layout window If I want to scroll the window up and down arrows are not working. For small scroll also I need to use zoom In and zoom Out. Can you tell me any solution for those.
Regards,
Bala
Hi,
I am working on a standard cell design. Once I do the characterization, I am noticing that the cell area = '0'. To avoid this, I am manually calculating the area of my cell and entering into the userdata.lib and read the same at the time of characterizing my cell.
When I go for a larger number of cells, how do I automate this?
OR
How do I read the area information from a lef file and write it to the userdata.lib automatically?
-Baranidharan
Hi,
I am trying to use the real time tuning feature in ADE explorer. However, every time I change the value of a variable, all updated plots have different colors than before. This makes it difficult to follow the results when there a lot of plots on screen. Is there any way to fix this?
BR,
/Imad