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cds_srr() mex file exception

January 27, 2019, 9:34 pm
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Hi,

I am using the matlab cds_srr() function to characterize the devices for my process. I sometimes get the following error that causes Matlab to crash.

Unexpected Standard exception from MEX file.
What() is:std::bad_alloc
..

Error in CdsSRRManager/read (line 24)
            [varargout{1:nargout}] = cds_innersrr('read', this.objectHandle, varargin{:});

Error in cds_srr (line 44)
    sig = CdsSRRManager.getInstance().read(dirname, p.Results.dataset, ...

Error in techsweep_spectre (line 64)
            struct_p = cds_srr(c.outfile, c.sweep, params_p{1});

 
Your MATLAB session has timed out.  All license keys have been returned.
Info, MEX-file cds_innersrr is being unloaded

Can someome please provide me with some assistance as to why this error occurs?

Thanks!

Sincerely,

Adithya

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Multiple Virtuoso/Spectre sessions sharing the same simulation folder - possible ?

January 28, 2019, 1:30 am
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Hi,

what BAD can happen if multiple Virtuoso/Spectre sessions are sharing the same simulation folder ?

In our project environment, we are using SOS workareas for revision control. The pointer to the simulation folder is a link to an special, non-managed folder.

In order to be able to run an older version of the project, we can simply copy the SOS workarea and roll back to any previous version of the design - still the pointers to the simulation folder remain the same.

Now, in case the user opens 2 Virtuoso sessions - one in the current workarea, one in the "rolledback" workarea, and he runs simulations in both of the sessions - and the names of the libs and cells are the same in both workareas - does Virtuoso recognize that the other session started already a simulation "Interactive:10", and the other session will start the automatically a simulation with "Interactive:11" ?

Or does it crash for some reason ?

Of course I can check it out myself (which I would do eventually), but maybe Cadence already built in a feature for such issues ?

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Unwanted empty line in Annotation Setup

January 28, 2019, 4:57 am
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Hello people,

I have a small annoyance with the annotations. Basically, I have an empty line between two cdf Component parameters I would like to annotate, but I can't understand where this line comes from.

See the attached picture. The unwanted line is between "l" and "totalM"

Any idea where this empty line comes from? It is fairly annoying.

Thank you and best regards,

Patrik

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trig and targ timing in measure report while using spectre and simulation trace report

January 28, 2019, 8:41 am
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Hi,

I was wondering if there is a way to report the time of actual measurement when trig and targ happened. I currently get the measures but have to trace back what time the trig/targ might have occured.

Also wondering if there is a way to get the percentage simulation time trace like 10% done 20% like that. My simulations run for couple of days and sometime it runs out of memory or lsf-wall clock time out. But then I have to load the waveform to get the info how far it went before the simulation died.

Also if there is a way to get the measures reported for however far the simulation was able to run.

Satendra

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Convert hspice function in Virtuoso

January 29, 2019, 2:36 am
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Hi all,

Currently, I have a hspice netlist and it contains some expressions in hspice syntax.

Example for a parameter:

ad='w<259.9e-9?(floor(500e-3)*(91e-15+w*120e-9)+(500e-3-floor(500e-3)!=0?91e-15+w*60e-9:0))/1:(floor(500e-3)*(460e-9*w)+(500e-3-floor(500e-3)!=0?405e-9*w:0))/1'

Is there any way so that Virtuoso can execute kind of this parameters?

Thanks and best regards,

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Annotations are just way too overpowering

January 29, 2019, 7:51 am
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I often stare at schematics for hours looking for the cause or solution to some very subtle issue and it is helpful to see some simulation annotations in the process. My issue is that turning on annotations produces an utterly overwhelming amount of clutter (including vast amounts of overlapping text and redundant information) and it's just too much for my feeble brain to take in while I'm keeping my concentration focused on the schematic itself. I know you can turn on and off "clusters" of information, but in my entire career I've *never* needed/wanted to see the full spread of voltages or parameters for *every* *single* component in my schematic.

For node voltages, I'd be delighted if only the net labels I placed on wires/nodes that I cared about lit up with their voltages beside them. Can this be done? Also, is there a way to create something like a note that I can place anywhere on the schematic whose contents can evaluate to stuff based on simulation results e.g. the current temperature and sum of the drain currents of mn1, mn2?

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instances based simulation tolerance setting

January 30, 2019, 4:12 pm
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hello experts,

we are playing Spectre simulator with very high precision circuits so naturally we need very tight tolerance setting, e.g., 'reltol 1e-6 'vabstol 1e-8 'iabstol 1e-14. on the other side, the translated digital signals or testbench signals not necessary to work for this hard at all. with the simulation running, it's easily run into convergence problem due to this unnecessory tight digital signals or testbench signals.

so wonder if I can set design dependent tolerance so that the real critical analog circuit works with tight tolerance, but not anything else?

thanks,

David

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Netlisting of post-layout simulation is very slow

January 30, 2019, 7:02 pm
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Hello, I have run Assura QRC on my layout, and obtained an av_extracted view for post-layout simulation.

Unfortunately, when I change my top-level cell view to av_extracted in the config file for the simulation, and I do Netlist&Run in ADE L, the netlister seems to work very slowly.

It prints "generate netlist..." in the CIW, and the progress bar moves by 1% in around 5 min, so at this rate I will need to wait 8 hours before netlisting is done. That is before the actual simulation, so I am even more worried about the time it will take for the actual simulation...

My design is not very complex (it's like maximum 10 transistors, two capacitors, padframe, a few resistors). I assume that people with far more complicated designs would take even longer to netlist, which seems impractical. This is why I am wondering if there isn't some setting I am not using correctly, or if there is a bug in the netlister. The size of my av_extracted view is around 50 MB, is that considered too large for the netlister?

My software version is Virtuoso 6.1.5-64b.

Thanks for any help and suggestions.

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Monte Carlo simulation: there are two peaks

January 31, 2019, 1:46 am
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Below are my setting and the curves.

You can find that, there are two peaks on the right side curve.

I really don't have idea why it has two peaks.

Thanks.

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Plotting gain versus output range

January 31, 2019, 6:12 am
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Hi everyone,

I am currently designing an OTA, I have achieved my specs but I wanted to examine how the gain of the OTA depends on the output range. How can I plot gain versus output range?

Kind regards,

Nicolas

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Characterization of a transmission gate (Liberate)

January 31, 2019, 9:21 am
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Hello,

I am trying to characterize a basic transmission gate (nmos and pmos in parallel, with complementary select signals, unbuffered input and output) with Liberate.

The thing is since the input is unbuffered, the input capacitance of the gate is assumed to be very large and as a result, when doing the P&R flow, the delays are very high (it takes the high values in the timing tables).

I recently read in the Liberate RAK that a TGATE is considered to be an analog cell an should not be characterized, but I am wondering what would then be the process to get its timing information for my P&R flow?

Best,

Edouard 

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Bus-expansion-like trick for an array of design variables

January 31, 2019, 10:56 pm
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I am using IC 5.1.

I create 64 voltage sources by first creating a single one, then copying it, pressing F3 and then entering 63 in the "columns".

I assign 64 net names by using bus expansion so then i get something like inp<0>, inp<1> ..... inp<63>.

The tools allow me to do the above quickly without manually having to draw so many voltage sources or naming so many nets one by one.

So I was wondering if there's a way I can assign 64 such design variables to the 64 dc voltage sources, lets call them inp_var<0>, inp_var<1>.... inp_var<63>, without having to manually pull up the property box of 64 voltage sources and typing 64 design variable names. Is there a quick way to do this, something like the above bus-expansion way?

Or is the only alternate way is to modify the netlist every time (using some script) before I run monte-carlo simulations for each combination of the 64 voltages? Or any other faster/better solutions?

I think this can be done in IC 6.1 but unfortunately I've to work in IC 5.1 because of legacy circuits, so please let me know if I can do it in IC 5.1. Thank you.

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ncvlog netlist generation

February 1, 2019, 10:47 pm
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HI,

I have schematic of transmitter, which has several blocks, which consist of functional view.

For one block (say BlockA), I have synthesized netlist with all cell definitions.

I am trying to generate the top level verilog netlist using ncvlog, I did below steps.

Created config view, and bind the  BlockA with symbol( My plan to pass the definition from out side)

and generate the netlist, it create the netlist but ignoring the blockA.

Could you please let me know if I am missing something here to netlist.

Thanks,

Nasser

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SpiceIn- MOS size matching problem

February 2, 2019, 3:24 am
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Hi,

I'm trying to transfer the spice netlist to schematic, and I adopts the SpiceIn (VirtuosoR 6.1.5).

However, the width and finger width are not the same to the input netlist file.

The following are  netlist and settings.

  • Netlist



  • Spice In setting
    Because I want the Finger Width and Width in CDF parameter to be the same,  I map W to Wfg and W together.
     


  • The SpiceIn.log 





  • Schematic



I found that the Finger width and Width are not the same and not as same as the netlist file, which would lead to LVS (netlist vs. netlist) error .
Could you please let me know if I made something wrong.


P.s. I also tried another version of Virtuoso (6.1.7), and the settings are as same as described before.
Both Width and Finger width is set to the min width of the PDK.
(Length is still correct, i.e. length is as same as netlist file)


Thanks.

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Custom Independent Current Sources

February 2, 2019, 12:42 pm
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Hello everyone,

I apologize in advance in case the question has already been answered

in a previous post (nonetheless, I would much appreciate a "pointer" to

the corresponding thread). Anyway, here's the problem:


I am relatively new (4 months) to Virtuoso (version 6.1.5-64b), ADE and Spectre and I would like to

custom-define and double-check with Spectre some independent current sources, namely by

using e.g. "iexp", "isin", or "ipulse" "ipwl" "ipwlf" etc, and perform an AC analysis with Spectre.


In particular it would be helpful to add e.g. simple current sources with the following behaviour in Laplace domain:

I(s)=A/(1+s*tau)

where "A" and "tau" are known.


Which is the best way to do it  by using the aforementioned sources?

Is there an easy way to achieve it with e.g. "iexp" or "isin" by setting the

corresponding damping factor (from e.g. tau=RC for the corresponding -1/tau pole)

and A (from the DC Current) directly inside the source? Are there any

step-by-step tutorials/guides? Do you recommend a different approach?

I tried by plugging both values e.g. in "isin", setting a "starting" frequency,

an arbitrary value for AC_magnitude (which should be "modulated" by

the damping factor) in the source panel, launching ADE and setting AC for a

target bandwidth, running Spectre, ... but I'm not getting the correct shape.


Some help panels are unfortunately not completely helpful, since they

mostly provide the same information stated in their corresponding

Property Panels for the (analog_lib) symbols, without further details.

Any help would be greatly appreciated


Best,


Stefano

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for the frequency range

February 3, 2019, 11:00 am
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hello,

can anyone suggest m how I can identify frequency range of any digital combinational circuit, there is any method which we can identify the range which circuit works because this is a very tedious job to check every frequency one by one ??

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Reliability analysis issue - ADE L tool

February 4, 2019, 8:19 am
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Hello colleagues, 

I designed a simple ring oscillator circuit using the GPDK045nm library provided by Cadence Online Support. 

Using the following tools on Cadence (ic6.1.6) - Spectre (12.1.1.096.isr12):

  1. Virtuoso schematic editor (IC6.1.6-64b.500.1).
  2. Lunch the ADE L tool to run Spectre simulation for:
  • Transient analysis.  
  • Reliability analysis. 

The transient analysis worked successfully and the waveform plotted using the ViVA XL tool.

The reliability analysis does not work correctly using both simulator modes:

  1. The RelXpert mode:

Error (RELXP-375): 

'The RelXpert simulator is unable to find 'RelXpert parameters in all model cards' to perform the calculation. Check if 'RelXpert paramters for some model cards' exists in 'input.scs' or 'correct syntax for reliability model or analysis is used in the netlist' before running the simulation again. Refer to RelXpert user guide for correct syntax. Failed to run RelXpert netlist preprocessing).

  1. The Spectre Native mode:

The waveform window should show some difference between stress and 10_years_aged but it is been overlapped. Also, in the ADE L tool - the Results -- Reliability Data is hidden. Here is the logout file warning:'Warning from spectre during transient analysis `rel-000_tran_stress', during Reliability Analysis `rel'.
WARNING (SPECTRE-16775): Can not generate the aged model because the aged device is missing or all device age values are less than the minage value in Spectre native reliability analysis flow'.

Q1) Do you know how the reliability models could be acquired and where should be added to the design before running the Spectre simulation?

I tried a different library and I received the same errors and warnings for the same circuit and others.

Q2) Is it possible to edit the netlist from the ADE L tool? I tried to edit a netlist from the netlist file but if I run the simulation, it will ignore what I typed and execute the options in the ADE L i.e. transient analysis stop time: 10n in ADE L and 15n in the netlist file. Spectre Simulation will execute the 10n as in the ADE L.

Looking forward to your prompt response.

Regards, 

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Where are Layout layer sets saved?

February 6, 2019, 6:56 am
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I created a number of custom layer sets in Layout XL but they aren't showing up anymore.

However, if I create another layer set with the same name as an old one, the name of the new one will have a "(2)" or "(3)" appended to it which indicates the originals are still saved somewhere.

Is there a way of loading the old sets or deleting them so I can recreate them without the appended numbers in the name?

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Virtuoso Chip Assembly Router in 6.1.8

February 6, 2019, 2:51 pm
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Hello,

I am having issues with starting up VCAR in 6.1.8 as mentioned. I was wondering whether this feature has been changed in this IC release. When I was using 6.1.6 the VCAR GUI window used to startup when launching it through layout XL like its shown below. 

Now when I try to launch it through Layout XL, I am getting the following error in the CIW when I press ok in VCAR Startup setup window.

 # Exiting because of license failure

Does this mean that during the upgrade to 6.1.8 from 6.1.6, a necessary license file was missed? Does the feature require separate licensing?

I am also able to do some Automatic routing of my nets from the Route pulldown menu in the Layout L toolbar. How is this feature different from VCAR?Is the only difference here that VCAR requires a rules file? 

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Virtuoso plot cannot adjust scale

February 6, 2019, 11:44 pm
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Hi

I'm trying to plot my schematics (heirarchically ideally) and the options under the plot (Plot Options) have the scale and center plot/fit to page options grayed out.  Is there something I need to change in my cdsplotinit or something?

Thank you

Chris

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