Hi All,
I find one difference between assembler and adexl is: when you want to add variable in test of assembler, the pop-up window is simple, including only "variable name" and "variable value". But in adexl, the pop-up window has more options, like you could add, delete, change, copy from and copy to ....
Actually ADE explorer still keep such feature.
So my question is, how to change setting to let assembler also has such feature, and no need to switch to ADE explorer view ?
BR
Hello,
I am using Virtuoso version IC6.1.7.
I make a Monte Carlo simulation in Assembler. I have vector (wave) and sclar (single point) outputs. For example in a DC simulation with temperature sweep:
vectorOutput = VS("\vout")
scalarOutput = VDC("\vout")
where vout is a net name. In results tab, I see all my scalar outputs listed. However, I do not see any vector outputs or waves (I do select "See Waveforms (Simulkation Data)" and "Save Statistical Parameter Data"). When I click on the "PlotAll", the vector outputs are plotted if I can plot them before closing Assembler window, but all of them at a time, not one by one separately as they do not appear in the list on results tab. If I close Assembler window and open again, the vector outputs are not plotted even if I click on "PlotAll".
Another problem is about deleting the different subwindows on visualitazion window. I have many outputs that are plotted; all at the same time when I click on "PlotAll". To have only the outpout I want to see, I need to select all the other subwinows one by one and delete them. This takes so much time.
My questions are the following:
1) How do I see the list of my vector outputs in the results tab in Assember when I run Monte Carlo?
2) How can I plot only a single vector output at a time?
3) How can I make Assembler plot all vector outputs after I close and reopen Assembler window?
4) How can I select many subwindows at a time and delete all of them?
5) How can I pre-define the number of sub-windows which outputs should be plotted on which subwindow?
Many thanks in advance.
Best regards,
Can
I am on 6.1.7.
I've been away from Virtuoso for a number of years and now need to create Rev marks, etc but find no way to do so in the newest version of the tool.
It used to be that there was a PG text script so the layout designer could easily create copyright, rev marks, etc.
What happened?
Is there an equivalent solution in the 6x versions?
Do I have to go find an ancient program and try to make it work?
Yes I suggest Cadence add this in the Tools Menu!
Katy
Hello, have a question about pnoise simulations noise type time domain.
I have a capacitor that is periodically
- initialized with a starting voltage (with a switch);
- charged with a current source (pMOS)
- and discharged with another switch.
The periodicity of the voltage across the capacitance is 2ns.I made a tdnoise simulation choosing a set of time-points during the voltage ramp across the capacitor. I chose the top plate of the capacitor as output node in the pnoise. The result does not convince me at all. Specifically I have 2 questions:
1) Why the x-axis of the integrated output noise is called "timeindex" and not time? And why it stops at 1.8n, while the pss stops at 2n?
2) The shape of the integrated output noise is not as expected. I expected a step of kT/C noise during the initialization, an increasing noise with a ramp (thermal noise integration) during the voltage ramp and a flat profile during the reset. As you can see in the picture below (pink=voltage across the capacitor, green=integrated noise), the green curve stays flat during the voltage ramp.
I upload also my settings for the pss and pnoise.
Thanks a lot for any feedback!
Hello,
I am looking for a way to optimize existing layouts. Many layouts have too less vias on nets with a higher current (e.g. power nets). Maybe there is an easy built-in function in Cadence Virtuoso Layout Suite to do the following:
Clearly the last point is very tricky because tool has to evalute the layout in every direction whether it is possible to extend the metals without creating DRC errors or shorts.
Does somebody knows a way?
Frank
Below's the exact violation I get. How can I fix it?
FATAL (SFE-2218): "/users/Projects/alpha/models/bsim-cmg_110.00/benchmark_test/modelcard_ak_verilog.nmos.lib" 206: It is not permitted to alter the paramerized module for the instance (`Mmain') currently.
Some background:
1. I downloaded the BSIM-CMG Verilog-A model. Then I followed the instructions from Andrew Beckett in this post 1332112 to create a simulatable cell cell. Everything works fine.
2. I made some edits to original BSIM-CMG model file (added additional white_noise to drain current in bsimcmg_body.include). This works fine the first time I simulate.
3. When I make any edits to my schematic (either related to the cell) or edits to my ADE-L testbench (e.g. change the SP simulation frequency range), I get the error listed above.
4. If I re-save the bsimcmg_body.include file, then I'm able to simulate again without issue.
I don't want to have to re-save every time I make a change in ADE-L or the schematic. Please let me know what I'm doing wrong.
Hi,
I'm trying to make a netlist with si. I've created my si.env
simLibName = "myLib"
simCellName = "mySch"
simViewName = "config"
simSimulator = "spectre"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("veriloga" "ahdl" "spectre" "schematic" "netlist")
simStopList = '("veriloga" "ahdl" "spectre")
simNetlistHier = 't
nlFormatterClass = 'spectreFormatter
nlCreateAmap = 't
simNetlistHier = t
All my bus signals looses their brackets (myBus_1 instead of myBus\<1\>).
Which option do i need to keep the bus format?
Best regards,
Christian
Dear all,
When I have a stimulus file, I can run well with the simulation performance mode: spectre. After running I can plot all the waveform. But when I use the simulation performance mode: APS, I can't plot the signal waveform in the stimulus file after running. The net in the stimulus file I write: ([#...] 0).
Hi,
I want change the order on hierarchy descend. By default , it is schematic,symbol. I want to change it to schematic,extract,symbol.
I tried changing the viewNameLists using this cmd:
envSetVal("constraint" "viewNameList" 'string "schematic extracted_lvs symbol")
But it did not help.
If I edit the Options->Editor ->ViewNameList, it works but only for the current schematic that's open. I want this for all.
Satendra
In the "Getting The Most Out Of Spectre APS" application note, slide 11 recommends
"For RF analyses – If Spectre 17.1 ISR11 or newer, use HPA and setthe environment variable SPECTRE_RF_POSTLAYOUT_EAP to 1 – For older versions of Spectre, use Legacy-RF RCR"
I have confirmed that I am using Spectre 17.1 ISR11 (specifically that release); should I be able to query this environment variable from the CIW with getShellEnvVar("SPECTRE_RF_POSTLAYOUT_EAP")?
Also, is setShellEnvVar("SPECTRE_RF_POSTLAYOUT_EAP=1") in the CIW the correct way to set this?
Lastly, what does this environment variable do and is it a recommendation or required to use the new +postlayout with SpectreRF?
Hi all
when I use IC616 base version above,(include IC616 HOTFIX,IC617,IC618) in GLOBAL Founderies 0.13um generic and 0.11um true shrink process,
Spectre netlisting often report error "
ERROR (SFE-23): "input.scs" 219: The instance `R3<3>' is referencing an undefined model or subcircuit, `ppolyf_u_pcell1575840381548207108'. Either include the file containing the definition of `ppolyf_u_pcell1575840381548207108', or define `ppolyf_u_pcell1575840381548207108' before running the simulation."
the subckt define as below
// Library name: gf11baseline
// Cell name: ppolyf_u
// View name: schematic
subckt ppolyf_u_pcell1575840381547973831 PLUS MINUS B
parameters segL=2u segW=2u
R0 (PLUS MINUS B) ppolyf_u l=segL w=segW
ends ppolyf_u_pcell1575840381547973831
// End of subcircuit definition.
Sometimes the names match,sometimes not.
But in IC616 base version ,they always match.
Could someone tell me how to fix this problems in IC616 base above.
Thanks.
Dear all,
How to set bindkey being able to toggle between maestro tab and schematic tab in assembler ? Also similar feature to toggle between Outputs setup and results tab ? As shown in the pic following.
By such way, you could save many time to manually switch between them.
Thanks
BR
Hi! Is it possible to avoid the "Open Configuration or Top CellView" dialog when opening a config view from the library manager? Instead, I would want it to just open the config view.
(there is a seemingly-related solution here, but after closer inspection I believe it's not related to what I'm talking about)
Thanks and regards,
Jorge.
In the QRC Techgen manual (extTechgen.pdf) it describes how stamped regions like well/substrate can be broken into regions around each substrate tap using stamp=2 in the layers_setup file.
I think I have this working with Assura LVS and was wondering if this can also work with PVS LVS? The Techgen manual only describes what happens with Assura geomStamp regions.
I gave this a try with the foundry PVS LVS deck but I think I need to create a modified deck to get it working.
Thanks,
Robin
Hi,
I am designing clock and data circuit, I want to do jitter tolerance analysis in cadence, how to run the simulation? Is there any guide or reference to do jitter tolerance analysis in cadence virtuoso?
I am using IC5 and IC6.
Thank you.
Hello,
I am not sure if this is the right forum to post issues regarding Quantus QRC. If it isn't kindly, move the thread to the appropriate forum.
I was trying to use Voltus FI for EMIR analysis. The rak is titled "Voltus-Fi-L EMIR Analysis Workshop". The basic flow has you do LVS with PVS followed by extraction using Quantus QRC's PVS interface. This is then used as an input to Voltus FI. The LVS ran without any issues but I get the following errors during RC extraction.
ERROR (CAPGEN-41313): The options "-delta_gate_ckt" OR "-delta_gate_ckt_by_device" OR "res_gate_factor/res_gate_default_factor" can't be used together "exclude_gate_res". Restate input options.
ERROR (RCXSPIC-27225): /public/cadence/618/EXT182/tools/extraction/bin/64bit//capgen failed with status 25
For what it's worth I am using EXT18.2 version, not the 18.1 version. The drop down menu in the layout editor now says Quantus instead of QRC like it does in the rak.
Hi,
All I want is one single curve of I/Q image rejection of my I/Q downconversion mixer with some random mismatch ...
I have to use ADE XL for that (ADE doesn't work) and I am confident I am doing everything right: I enabled the Monte Carlo corner, have an output "IRR4" at 100 kHz and "IRR4_f" which would give me a curve vs frequency in a normal ADE simulation. I hit Run -> Monte Carlo Sampling and make sure I have selected [x] Save data to allow family plots.
At the end of the run I can plot histograms etc with "IRR4" but the data for "IRR4_f" does nowhere seem to be accessible. The results just show "IRR4".
Where are the curves over frequency?
Ideally I would do 100 monte carlo sims and get 100 IRR-vs-frequency curves on top of each other.
I attach screenshots.
Thank you!
Hi! Very often I export my ADE-XL simulation results in .csv files, and when I click on them in the ADE-XL window it launches my web browser (firefox) to try to open them. Is there a way I can set it to use LibreOffice instead?
Thanks and regards, Jorge.
Dear All,
I saw the Cadence-post (please see at the end of this post) titled:- What is difference between "node" and "nodetoground" captab output, and how to access captab results.
It says that one can use the OCEAN command 'pv' to find the node-to-node and node-to-ground capacitance.
I ran a dcOP analysis and then I opened the calculator. I typed pv("/I0/ref_core/in: vssa" "Fixed" ?result "captab"). /I0/ref_core/in and vssa are two nodes in the schematic.
But, it did NOT show any value in the calculator. Perhaps I am missing something.
Could anybody please tell how to use the OCEAN command 'pv' either in calculator or in OCEAN script to find the captab results.
Kind Regards,
What is difference between "node" and "nodetoground" captab output, and how to access captab results
You are using the captab option with dc or transient analysis in spectre. This gives a table of node capacitance for the circuit. You can choose either "node", "nodetoground" or "nodetonode" detail options for this table.
"spectre -h info" gives following:
***
9 detail=node
How detailed should the capacitance table be?
Possible values are node, nodetoground or nodetonode.
***
What is the difference between the "node" and "nodetoground" ?
How to access capacitance values from captab results?
The "node" capacitance is the total node capacitance, which is the sum of node to ground (reference to ground) capacitance, and node to other nodes (reference to other nodes) capacitance.
So, if I have this topology
c1 (NODE 0) 5pf
c2 (NODE a) 1pf
c3 (NODE b) 2pf
and there are no other capacitances, then
"node" capacitance for NODE is
5pf + 1pf + 2pf = 8pf.
"nodetogroud" capacitance for NODE is
5pf
"nodetonode" will list out c2 and c3 values of 1pf and 2pf.
The spectre netlist will contain something like:
captabInfo info what=captab detail=node where=rawfile
You can then use in ADE -> Results->Print Capacitance Table to access the captab results. You can also access the results in the Results Browser and calculator.
To access results in Results Browser, open psf/raw directory and check results created in folder like captab-info.captab.
To access results in calculator, you can use ocean ‘pv’ function something as mentioned below:
pv("NODE: NODE" "Total" ?result "captab")
or
pv("NODE: NODE" "Variable" ?result "captab")
or
pv("NODE: NODE" "Fixed" ?result "captab")
Hi,
Because I replaced my old display to be a high resolution display, all cadence CIW and LibraryManager label and menu fonts become very small. How can I make the font size to be larger?
My cadence version is IC5141.151. I tried to put "hiSetFont("CIW" ?size 20)" into my .cdsinit file. but IC51 says there is syntax error for it.