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Cell Abutment Wiring Warning !

January 2, 2019, 6:39 am
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Hi,

I am using Virtuoso XL for my layout. The abutment sever as well as auto abutment are enabled in it. When I abut the existing Pcells, let's say 2 PMOS devices like below, abutment works just fine. 

When I check against the source (schemaitc), I can see following messages :

INFO (LX-1005): Parameter 'rightAbut' is set to '0' on schematic instance 'PM11' but is '3' on layout instance '|PM11'.

INFO (LX-1005): Parameter 'rightAbut' is set to '0' on schematic instance 'PM6' but is '5' on layout instance '|PM6'.

(I usually update the schematic components later to match layout and schematic)

However when I connect the abutted contact to another (similar) node, the yellow box appears on the abutted contact. What is the reason for that ?

Thanks

Ranaya

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Cadence Liberate Characterization of Complex Logic Cells

January 2, 2019, 12:48 pm
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Hi,

I am trying to characterize a combinatorial circuit which has 5 (A, B, ...., E) inputs and 3 outputs (X, Y, Z). As per the cell behavior, output Z does not depend on input E. When I perform the characterization without user defined "define_arc" s, the process fails trowing following error :

ERROR (LIB-54): Some output transitions did not cross both 'measure_slew_*' thresholds for arc of cell:'UTCOMX', r_pin:'E', r_pin dir:'r', pin:'Z', pin dir:'r', type:'combinational rise_transition' when: (!D * A * B * !C). To debug, review the saved simulation results for deck: delay_21. Possible solutions include setting 'extsim_exclusive' to 1 and 'sim_estimate_duration' to 0 with increased 'sim_duration' as needed, and rerun.

My questions are :

1. Can we use define_arc in following format to include only valid logical states [ in this case removing E (-related pin) to pin Z (- pin)] for the given cell ?

//Assume that pin_list order is A B C D E X Y Z

//define_arcs for A -> Z transitions
define_arc \
- vector {RXXXXXXR} \
- related_pin A \
- pin Z \
UTCOMX

define_arc \
- vector {RXXXXXXF} \
- related_pin A \
- pin Z \
UTCOMX

//Same routine goes for B -> Z, C -> Z .... and other combinatorial states except E -> Z !

2. In 1.) case, let's say we do not specify "- type" (i.e. hidden, power or delay) inside define_arc ! Does Liberate still calculate hidden, switching power and delay values for each define_arc state automatically ?

3. Is there an easy way to exclude E -> Z monitoring without specifying the define_arcs manually for all other states ?

Thanks in advance

Ranaya

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COmmand to find Process Name

January 3, 2019, 8:35 pm
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Hi,

Is there any command in cadence skill to find the process name Like if it is tsmcn28rf or other proces nodes

Please let me know

Thanks,

Nirmal.

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how to find input impedance of common gate configuration

January 4, 2019, 5:34 am
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what is the general way to find input impedance of common gate amplifier stage. I tried to provide input as IAC mag =1 , trying to find the impedance at input node (Vin), trying to make it as(Vin/In) ,its coming as a gaussian distribution with peak of 95 Mega V at 300 Mhz.  I m running a system around 500 MHz, I m sure the for common gate amplifier input impedance must be low, but its coming like this. I m not sure whether my method is right or wrong.  for low frequency its coming around 350 ohm.

how to calculate generally input and output impedance .

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QRC Assura Extraction failing !

January 5, 2019, 6:58 pm
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Hi 

I'm trying to run parasitic extraction on Assura QRC, and the run is failing. The log file says that it couldn't get the library models for the NMOS, PMOS. Something like this:

My setup is as follows:

Can someone tell me what's going wrong?   ? 

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Placing of physical design into another physical design in innovus

January 8, 2019, 4:08 am
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I want to place physical design of memory macros that I have created separately in another main design in innovus..

How to do that??

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Layout editor: quick align "Move/Stretch" mode deprecated in ICADV?

December 15, 2018, 7:53 am
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Hi! The "Move/Stretch" mode is not available in my layout editor (L) in ICADV 12.3.  Here's a comparison of what I see in IC 6.1.6 (28nm PDK, left) and ICADV 12.3 (16nm PDK, right):

Moreover, the Layout Editor L documentation for ICADV 12.3 still mentions this mode (p.1086 of the user guide)... is my setup (or PDK) broken? has this mode been deprecated?

Thanks in advance for any help!

Regards, Jorge.

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tran statement in spectre

January 9, 2019, 6:58 am
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I have used the below commands for tran statement for 1000 point 

tran1 tran stop=4e-8 strobeperiod=4e-11
tran1 tran start=0 stop=4e-8 strobeperiod=4e-11

but strange, in  all print file i am able to view more than 1150 points. which is not required for my application.

can i get a correct trans statement for 1000 points,

can be considered the above range.

Regards,

Manjunath N

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Plot RMS noise over time with AMS simulator

January 9, 2019, 2:50 pm
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Hello everyone,

I have a delay element made of a current source (pMOS) + capacitor towards GND. I would like to plot the RMS noise on the capacitor over time, after running  a AMS simulation 

I know it is possible to visualize the rms noise over time with a pss+pnoise in specific time instants. But with AMS I can only run Transient Noise or Noise analysis. Also, it seems there is no Multiple Runs option for Transient Noise with AMS.

Since the overall circuit is quite complex and non linear, I was thinking to run Transient Noise and to use the calculator, like the example here. However that one is with Multiple Runs, but I don't have that option.

Do you know how to do it?

Thanks 

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spectre +aps simulation: the vsources devices with dc=0 are removed, so the currents through those devices cannot be plot

January 10, 2019, 12:35 am
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Hi there,

I have next situation: in some schematics are some vsource(s) used just as nets separators or to probe the currents. In most of the cases type=dc.

They are preferred by designers versus iprobe, because vsources symbols are smaller and do not overlap neighbor wires.

The problem is that when we use spectre +aps, the currents through vsources without voltage ( or dc=0) are not saved.

The iprobes are fine, but as I said the vsources are preferred by some people.

I assume that +aps is doing some netlist optimization, removing the dummy devices. I've already read https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/37112/not-to-remove-instances-whose-terminals-are-connected-together .

I have some questions:

- are the vsources with dc=0 considered as dummy devices?

- is there any possibility to preserve all instances of a specific type? From the above thread I've understood that we can preserve all insts, or selected insts.

- where I can read about the optimizations done by aps and what are the side effects? I assume that speed is coming with a price.

Simulator version: mmsim/15.1.0.isr17

Below is a screenshot of the schematic and the associated netlist. I can probe the currents through bot iprobes and through V3, but not through V1 and V2.

If I remove +aps argument from spectre command line, then I can probe the currents through all vsources too. 

Thank you,

Marcel

 

IPRB2 (net020 net021) iprobe
IPRB1 (net024 net023) iprobe
V3 (net021 net019) vsource dc=100.0m type=dc
V2 (net023 net020) vsource dc=0 type=dc
V1 (net017 net024) vsource type=dc

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vsource parameters cleared when changing source type

January 10, 2019, 7:07 am
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Hello,

I am experiencing an issue with the vsource from analogLib.  If I change the source type then then all the previously entered parameters in the form are cleared. I am remembering from past experience that the form should remember prior parameters so that you can switch back and forth between source types without having to re-enter them all.

It might have something to do with our site setup.  Any thoughts on where I could look?

Cheers,

Phil

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schematic search/replace criteria combination

January 11, 2019, 10:39 pm
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Hi guys,

     I am trying to do such replacement in schematic hierarchy: change all libName_A/cellName_A to libName_B/cellName_A, which means I need to combine libName and cellName together when I do search and/or replace. Anyone know such feature ?

BR

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Monte Carlo analysis on schematic Vs post layout

January 13, 2019, 6:18 am
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Hi,

Is it more appropriate to run Monte Carlo simulation on circuit schematic or on the post-layout extracted version?

Will the mismatches be captured more realistically if the analysis is run on the post-layout extracted version?

Thanks.

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OCEAN: How to Check if a Corner is Enabled/Disabled?

January 13, 2019, 1:29 pm
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Hi,

It is well described on the manual how to enable/disable corners. However I could not find a way to check when a corners is indeed enabled or disabled - since all corners are returned from ocnxlGetCorners() function.

Thanks for the support.

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Stability and transient analysis do not match

January 14, 2019, 1:41 am
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Hi all,

I'm using virtuoso subversion IC6.1.7-64b.500.21 and spectre subversion 18.1.0.143.isr1.

I'm verifying stability in a nested multiloop LDO design, so I've introduced several probes to analyze each of the existing loops individually. The location of poles varies with the load current so two runs are made, one for no load and one for max load condition. One of the loops is showing me -40 degrees PM at high load condition but the transient analysis shows no oscillatory behavior. I know the iprobes from analogLib do not open the loop and should not be affecting the operating point of the circuit, but I'm having a hard time understanding what's the root cause of the different results and how to reconcile them.

How to make sure that stb results are reliable?

Attached you can see the simulation results. Let me know if anything else is needed (I show only a zoom in the transient response from zero to max current and viceversa)

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bindkey to display Assembler/ADE XL->options->save

January 14, 2019, 7:50 am
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Hi All,

    Is there anyway to define a bindkey to activate the pop-up window of Assembler/ADE XL->options->save?

    Thanks for your help!

BR

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per-test config variables in ADE XL

January 15, 2019, 1:51 pm
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I have two different blocks whose active view I need to vary in different ways and I'm hoping to find some guidance in the best way to do it. The first is an opamp in the circuit being tested.  I want to compare the performance of two variations on the schematic, say schematic and schem2.  I am using a config sweep variable to do this and it works well.

There is also a stimulus component in the test bench that has a voltage source and some passive elements.  I want to be able to set that as a sin wave for some test and a pulse for others.  I also want to vary the passive network involved (e.g. AC-coupled in one test and DC-coupled in another).  My stimulus cell has several schematic views (sch_sin, sch_step, etc.).  I had accomplished this by editing the switch view list in each test.

So I can imagine a couple of options, in decreasing order of preference.

1) Set a config variable for both and sweep it as a global variable for the opamp and specify the stimulus view locally to each test.  This is what I would like to do, since it seems cleanest and least error-prone, but I do not see a way to add config variables to an individual test.  Is there any way to do this?

2) Set a global config variable for the opamp and edit the switch view list for all of the tests.  This is basically what I described above, except that it doesn't work.  The switch view list seems to disappear from the environment dialog when I create a config variable. It's also a little more cumbersome than (1), but it would work fine.

3) Delete the config sweep variable and control both cells through the switch view list.  This is awkward because I would need to remember to edit each test if I want to change the opamp from schematic to schem2.  It also seems error-prone, because the view name intended for the opamp also affects how other cells are netlisted.

Is there a way to do 1 or 2?  Is there an option I'm not seeing? 

Thanks for your help,

Jeremy

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include file in subckt in ADE .

January 15, 2019, 6:33 pm
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My end goal is to get a netlist I don't need to touch. Is it possible to create an schematic_RCX view for a cell (regular schematic view) and add a component to that schematic which specifies a file to include in the netlist for that cell?

For example, when the netlist for the cell is created, the file will look like :

.........

subckt block_name ....
..........
// normal component lines
........

include "/path/to/user/specified/file"

ends block_name

....

// other component lines

 

Since there are components like PWL waveforms that can read files, this is of course feasible, but is it already available/easy is what I'm really after...

Thanks!!

I can not find the solution file ,pls give me the links

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Cannot select a layer. Layer-Purpose pair does not exist in LSW?

January 15, 2019, 11:30 pm
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Here is my problem. I've added an instance of a low-leakage nmos in the layout editor using 'Add Instance' menu. Now, that instance makes use of a layer called 'CPH'. However, the layer is written in red text in the LSW. And whenever I click on it, the following error message appears:

*WARNING* (LE-104017): The entry layer cannot be set to (CPH drawing) because this layer-purpose pair does not exist in the LSW (or the Layers assistant). Ensure that the layer-purpose pair has not been set to be excluded from the LSW.

Same happens when I click on that layer in the layout editor. So, once the instance has been added, I cannot move around this particular layer. Can somebody help me tackle this situation? Why could this be happening?

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Cannot run Assura RCX

January 16, 2019, 8:40 am
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Hello,

I am trying to do a post-layout simulation of a ring oscillator to determine why there is a discrepancy between the simulated oscillation frequency and the fabricated chip. Unfortunately when trying to use Assura RCX to do the parasitic extraction, I am unable to run RCX because the run button is grayed out. I have a successful LVS with everything matching and no errors. The help menu regarding RCX simply says that after a successful run of LVS, I can reopen the run and "Once the run is opened, the Run RCX... item is enabled in the Assura menu." However, if I open the run, there is still no menu option called Run RCX, nor anything that mentions RCX. I also found that if I attempt to run Assura from avview, the avview Assura Form also has "RCX -> Run..." grayed out as well as "Setup -> RCX setup..." grayed out. Does anyone have any idea what is wrong with my RCX? 

I have attached pictures demonstrating what I see.

Thanks,

G

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