I have two variables defined in ADEXL.
I want to sweep variable A, with Four values, 1,2,3,4.
Then I want to make variable B sweep dependent on A.
For instance, when A is 1, then B sweeps from 1 to 3. When A is 2, B sweeps from 3 to 5. When A is 3, then B sweeps to 6 to 9.
How can I achieve this? is there a way to use some logic expression in the variable definition?
Thanks!
Hi,
Even after completion of simulation(in output log showing successfully completed), in adexl state its still showing running state. But when i tried to plot those running state plots, im able to plot few signal but not all.
Thanks
Ashok
When I plot waveforms in ViVA, sometimes variables are included next to the waveform names in brackets.
Is there a way to disable this?
It makes the waveform name excessively long.
I've included an example below.
hello experts,
in Cadence IC6.1.7, the new feature of automatically snapping two close by cells to be perfectly overlapped to each other. but sometime we don't want that. we'd still want to keep more spacing to allow contacts/vias to be possible. how can we turn that feature off?
thanks,
David
I am running a transient simulation and would like to use Spectre MDL to calculate the fft of a signal. For correct processing, I need to change the value of the x-axis of the signal and in normal ADE or ADEXL simulation, I used to fix it using drPutWaveformXVec. Is there similar comment for SpectreMDL?
Regards,
Su Lim
Hello all,
Right now I investigate about a curious thing that happens when an user copied an adexl view.
I have two projects, which belong to two different business units of my company. Unfortunately, the people who setup the projects are already on Christmas holiday.
In the first project, when I make a copy of an adexl view, history items are still in the view, but they loose the reference to the directory with the simulation results.
This mean that, inside the data.sdb file, fields like resultsname, simresults psfdir, ... are empty: <resultsname></resultsname><simresults></simresults>. This behaviour is wanted.
In the second project, these fields are kept identical to the ones belonging to the original view. This is annoying because when one of our designer tries to delete a history item, the results of the original view are also affected.
Is there an environment variable which controls this behaviour? Or is is a callback which patches the new data.sdb? Both projects run ICADV 12.30.719
Any help is appreciated.
Best regards,
Patrik
Hi,
How can I change the tooltip text color from white to black?!
Currently it is white text with background red, hence visually it is not clear.
I want to change the tooltip text color to black with background red/white. Kindly let me know the procedure.
Thanks and Regards,
Bitan
I am trying to rotate a schematic symbol in place. Or, put another way, I want to just change the orientation of the symbol and not change the location of the symbol.
I have tried the functions below to achieve this but they all seem to translate the symbol to odd places:
Alternatively I could probably just save the previous origin location and put it back after the move but I wanted to understand what I am missing here. Anyway, thanks for the help!
(Bonus Points: I am trying to get this to work for something that would extract the underlying schematic from any given layout. So if you have any info that may help on this I'd appreciate it.)
HI everyone,
Can you help me?
I want to measure power of inverting summing using opamp.
however, i just use opamp model (written by verilog A) in adhlLib library.
so, i dont know, whether i can measure power consumption.
Thank.
Hello,
we usually enter full path of simulation model (e.g. /A/B/C/my_model.lib.scs) before start simulation.
I'm wandering: is there anyway to set a default path (e.g. /A/B/C) to spectre? Then I just enter "my_model.lib.scs" before start simulation and simulator will find model file under /A/B/C automatically.
the advantage of such a thing is: when i porting design from process X to process Y, i don't have to update model path (assuming exacting the same model name) for my saved state.
Thanks a lot.
I use the following command as:
hiRegisterBindKeyPrefix("Schematics")
hiSetBindKey("Schematics" "<Key>F1" "sevNetlistAndRun(sevSession(hiGetCurrentWindow()))")
My idea is similar as bindkeys for ADEL. But not work. Can you correct my idea.
Regards
All the simulator options is same between MMSIM13 and MMSIM15, for gmin=1e-14, the output ac response is different when the gnd is notconnected.
why?
HI Experts,
Needs some suggestion to automate the below flow, ( or may be you can suggest some better way)
Suppose we have multiple cell for inverters, and we have created respective function model of those cells.
We are ruing AMS simulation to verify the models, ( creating config view and running simulation)
I am looking a way to just create a one TB for inverter and it can run simulation for all inv flavor.
I have the amsDMV flow based on simulation results to verify the model correctness.
Thanks,
Nasser
Hi all,
I tried copying a p-cell from our tech library to a local library.
But the p-cell is copied as a normal cell.
Can anybody tell me how to copy a p-cell from one library to another library.
Thanks,
Ganesh Doddipatla.
I have such warning in my CIW:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
WARNING (ASSEMBLER-11301): The values of following environment variables conflict with each other:
spectre.envOpts controlMode 'batch'
maestro.simulation interactiveA t
Simulation will now be run in the interactive mode. To run the simulation in batch mode, set the 'maestro.simulation interactiveA' variable to nil.
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
My question: which mode I should use and how to set ?
Thanks
Hi everyone ,
I have made cellviews for each logic gates (and, or, xor ...) ,each logic gate has its voltage supply (Vdc) .
And, I have made many copies of this cell in my circuit ,such that there is not any Vdc in the final schematic containing these gates.
Finally, I want to measure power consumption in circuit as whole ??
Thanks
Hi all,
In my digital circuit, there are inputs port and outputs ports and I wonder if I can test the functionality of this circuit.
In the other wards, I want to put some inputs in a file in the form binary and get the output in the same form by defining the VOH and VOL.
thanks alot.
Hi, I know we could set "axlRunSimultion()" for adexl and so on, but for assembler, is there similar bindkey available ?
Thanks
Hello,
I use the following commands in my cds.lib file:
DEFINE my_category libs/my_category
ASSIGN my_category DISPLAY my_category_display
ASSIGN my_category COMBINE lib1 lib2 ... libN
as described in https://community.cadence.com/cadence_blogs_8/b/cic/posts/things-you-didn-t-know-about-virtuoso-library-manager.
Library manager appears as I expect, but I get lots of these warnings:
*WARNING* COMBINE attribute library not defined
library: 'lib1' file: '.../cds.lib', line: 118
is there a way to suppress them both using ADE and in ocean scripts?
Thank you
Best regards,
Aldo
I want to replace operation of RMB-Annotation-Design Default in schematic, is there any bindkey available ? Thanks.