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How to save Spectre tran results over just a specific period in a simulation

July 20, 2018, 2:13 am
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Hello,

I am running a spectre simulation from the command line and, as my simulation is large and extracted, I'd like just to save the tran results over a certain period. Not for the whole simulation.

My current command is

spectre ++aps +multithread -f fsdb VO15A_SERDES_TOP.sp -o /home/suppdm3/ANSYS/VO15A_SERDES_TOP

I haven't been able to find the option that I need to just specify say from "10ns to 20ns" for my simulation.

The call within my spectre.scs file is

tran tran stop=25n write="spectre.ic" writefinal="spectre.fc" \
    annotate=status maxiters=5

I think this must be a pretty easy option to define but I haven't found the right syntax.

Thanks for the help,

Matthew Cordrey-Gale

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QRC conflictiong name spaces

July 20, 2018, 6:14 am
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Hello,

I'm trying to generate an extracted view from a layout with QRC and, after selecting the LVS run to be extracted, I'm promped with the following message:

"You are about to enter names from conflicting name spaces
Do you want to continue?"

Either if I say YES or NO, I can see that there are some imprecisions in the extraction. Specifically, I have a poly1 plane in my layout, which typically is extracted with a huge capacitance toward the upper metals. Apparently this capacitance disappeared completely, without any additional warning from the CIW. The capacitance from the upper metal layers is simply reported to substrate (gnd), without considering the poly layer. This imprecision in the extraction is very critical as the poly-capacitance has a key role in my design - that's why I noticed the difference immediately - but I can't tell if there are any other problems with other layers.

Can anybody help me understanding what's going on, or can tell me what's the meaning of the warning message that appears when I launch the QRC?

Thank you,

Filippo

p.s.: I'm using Cadence IC6.1.5.500.132 and running the extraction with ASSURA 4.1_USR2_HF20 and Cadence Extraction QRC version 11.1.2-p106.

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How to setup and simulate differential TDR

July 14, 2018, 11:42 am
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Hi,

I want to do differential TDR simulation in cadence virtuoso. I have a differential channel, made of Tlines and interconnects (passive componenets). How to setup the TDR simulation to get impedance over time? I know, I have to terminate both n and p channel with 50 ohm each at the output. I have to do also in the input. But how to connect the step voltage source or pulse generator at the input and get the recuiredimpedance over time from the channel reflection? Can anyone help me.

Note: I am using virtusos version IC6.1.7-64b.500.4, there is no rflib. So I cannot use Balun ports.

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ADE XL new test addition on a running simulation

July 23, 2018, 8:14 pm
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How can I add a new test to an existing running ADE XL Simulation? Since it takes a couple of days to run the same I don't want to run it again , so if there is any possible ?

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Vgs exceeding in the PSS analysis

July 24, 2018, 5:20 pm
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I am doing PSS analysis to calculate the THD. I ran the simulation for all blocks separately and everything is fine, but when I place then as a chain, I receive a Vgs exceeding warning. I checked everything and nothing look odd but the Vgs goes to higher than 20 V while the supply voltage is less than 5 V. Surprisingly, I do not get this warning when I do the Transient simulation with the exact same setup. Has anyone faced this problem before?

My cadence version: IC6.1.6-64b.500.6

Thanks!

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Transient DC voltage setup

July 24, 2018, 8:20 pm
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Hi Team

I have attached 3 pictures concerning an issue of a spectre transient simulation. The first picture is what my test circuit looks like, which is in differential configuration. Each have 2 tones  and a DC value. The DC value are the same and 2 tones are 180 degree out of phase.   I marked the differential input with RED. then there is a pair of DC blocking caps. The voltage after it is marked as GREEN. 

The second picture showed that the the red plot is as what it should be: same DC and out of phase. But the circuit believe that two GREEN wires have different DC value initially and slowly get to its correct value. 

The third picture is the zoom in version of the second picture so it's clear the difference in DC valure  

I believe the cause of such plot is due to the initial voltage of the differential path are different. (in my case are RED at the begining ~470mV and ~463.5mV). This makes the circuit after the caps believe the DC voltages are different. I am trying to get rid of the settling time.

I have tried set ic in the cap to be 0V , and the ADEL-simulation-convergence aids-initial condition. Non seems able to get rid of the initial settling time (in this case, more than 420 ns of useless simulation) I could do something wrong. But can anyone help?

Thanks

Allen

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Using the Navigator in Virtuoso L

July 25, 2018, 11:32 am
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Very simple question...

When in Virtuoso L, using the navigator I can highlight a net that is open and needs to be routed. The problem is, as soon as I click in the layotu window the flight line goes away. Is there a way to keep the flight line on?

I am using Virtuoso 6.1.5

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Difference between V(P1,T1)

July 26, 2018, 3:51 pm
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Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A 

I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and 

V(P1) <+ V(T1) would mean potential difference between P1 to gnd is equal to T1 to gnd.

I feel these statements kind of means the same, but when I used these statements in 'if block' in 'Verilog A', use of each statement gives different results, can someone please explain what difference does it make between these statements.

Also, can we use these statements in an 'if block'?

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ade explorer set instance value

July 26, 2018, 4:17 pm
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hi,

i create one simulation in ade assembler, several  test for simulation, for example, i place one analoglib “port” in schematic, but different test need to set different port source type, like dc and sine, how could i to switch cross different test in ade explorer?

for PAC simulation, i need to check display small signal params and set PAC level( iknow ican set variable for this level), how can i to control check box? 

if checkbox is not cheched, and i set PAC level by variable, is this variable take effect?

thanks 

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how to generate spectre netlist for all the schematics in 1 lib ?

July 26, 2018, 6:21 pm
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Hi ,

I would like to generate spectre netlists for all of the schematic cell in my lib. What can I do ? 

I search in the forum but didn't the answer yet 

thanks 

Nhumai 

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Create a symbol from layout

July 27, 2018, 5:25 am
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I have created a symbol by momentum for a transformer in 65nm technology

but when i use mentioned symbol in a schematic and try to run LVS, but i have gotten error consider that the symbol could not read.

could anybody guide me?

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how to set a bindkey to display multiple layers ?

July 27, 2018, 9:39 am
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Hi, 

I am using cadence 6.1. I am trying to set a bindkey to display certain layers at 1 time. For example key '0' will display base layers, key'1' will display metal1 via2 and metal 2 . I have a simple setup like below but it didn't work. I am not sure what is the missing in this code ? I am new skill code 

thanks 

Nhumai 

hiSetBindKeys( "Layout" list(

 list("<key>1" "pteSetNoneVisible() leSetEntryLayer(list(\"M0\" \"drawing\")) leSetEntryLayer(list(\"M0\" \"pin\")) letSetEntryLayer(list(\"VIA0\" \"drawing\")) leSetEntryLayer(list(\"M1\" \"drawing\")) leSetEntryLayer(list(\"M1\" \"pin\")) leSetEntryLayer(list(\"CM1A\" \"drawing\")) leSetEntryLayer(list(\"CM1B\" \"drawing\")) leSetEntryLayer(list(\"prBoundary\" \"boundary\")) hiRedraw()")
 list("<key>2" "pteSetNoneVisible() leSetEntryLayer(list(\"M1\" \"drawing\")) leSetEntryLayer(list(\"M1\" \"pin\")) letSetEntryLayer(list(\"VIA1\" \"drawing\")) leSetEntryLayer(list(\"M2\" \"drawing\")) leSetEntryLayer(list(\"M2\" \"pin\")) leSetEntryLayer(list(\"CM2B\" \"drawing\")) leSetEntryLayer(list(\"prBoundary\" \"boundary\")) hiRedraw()")
 

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Export transient waveform into ASCI/CSV format for psfxl simulation data

July 27, 2018, 3:10 pm
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I used to use the psf function $CDS_INSTALL_DIR/bin/psf to output transient waveform into an asci format. Is it possible to use the psf function to do do this on a psfxl transient data? If no, is there an equivalent command that will allow me to do this? 

I am using ICADV12.30 with mmsim 16.10 

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Virtuoso L and virtuoso xl cost ?

July 27, 2018, 11:01 pm
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Hi All,

How much does Cadence Virtuoso L cost  and Virtuoso XL cost ?

Because I want to compare their prices.

Best regards,

Marben

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problem with resistor in corner analysis

July 28, 2018, 12:19 am
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hi i am designing a circuit (transimpedance amplifier ) that has a few resistors .. i want to do corner analysis and when i use resistors from tsmc library it gives errors and says that these resistors are undefined . when i use analogLib resistors corner simulation is done without error i already tried changing the resistor type to poly and adding ff_res ,ff_rfres_hri,ff_rfres_rpo,ff_rfres_sa but it didn't work i use cadence 6.14 can someone help me ?

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How to use rand_bit_stream for trasimpedance amplifier ?

July 29, 2018, 3:57 pm
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 hi i need to simulate eye diagram with cadence 6.14 for my transimpedance amplifier .transimpedance amplifiers input is current. i know i should use rand_bit_stream from ahdllib for generating random bits but its a voltage source and i need current source i saw that someone said Use VCCS but i dont know how to use rand_bit_stream with vccs because rand steam has 1 output but vccs has 2 inputs . another thing is how to make 2^31-1 bits i thought it means that we should do a transient simulation for 32767*period is that it? 

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Strange problem when working with small currents in ADE L

August 1, 2018, 2:14 am
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Hi,

I noticed a problem when simulating in ADE L with a 0.18um technology. For a simple current mirror, I found that results are not reliable for small currents (in the order of nA) if transistors’ parameters W and L are directly set. On the contrary, if the multiplier parameter is used, simulation results match with those expected. Moreover, for currents in the order of μA, simulation results are always as expected.

The schematic is this one:

Results of 10 DC operating point simulations are shown in these Tables. As you can guess by noticing the VDS,sat value, the level of inversion is kept more or less constant across simulations. For small current, only setting the multiplier parameter works. On the contrary, for higher currents, either using multiplier of directly setting the values of transistors work as expected. It is also worth noting that scaling the Lenght of the transistor instead of the Width WORKS both for small and high currents.

 

Sim 1

Sim 2

Sim 3

Sim 4

Sim 5

V0 [V]

1.8

1.8

1.8

1.8

1.8

I0 [nA]

5

5

5

5

5

R0 [MΩ]

20

20

20

20

20

W0 [μm]

0.5

0.5

0.5

0.5

0.5

L0 [μm]

0.5

0.5

0.5

0.5

0.5

W1 [μm]

0.5

1

2

0.5

0.5

L1 [μm]

0.5

0.5

0.5

0.5

0.5

multiplier1

1

1

1

2

4

VX1 [mV]

270.208

270.208

270.208

270.208

270.208

VX2 [V]

1.678

1.6722

1.593

1.558

1.328

VDS,sat1 [mV]

43.381

43.381

43.381

43.381

43.381

VDS,sat2 [mV]

43.381

43.223

44.632

43.381

43.381

Iout [nA]

6.11

6.39

10.33

12.08

23.58

 

Sim 6

Sim 7

Sim 8

Sim 9

Sim 10

V0 [V]

1.8

1.8

1.8

1.8

1.8

I0 [μA]

1

1

1

1

1

R0 [kΩ]

100

100

100

100

100

W0 [μm]

100

100

100

100

100

L0 [μm]

0.5

0.5

0.5

0.5

0.5

W1 [μm]

100

200

400

100

100

L1 [μm]

0.5

0.5

0.5

0.5

0.5

multiplier1

1

1

1

2

4

VX1 [mV]

306.559

306.559

306.559

306.559

306.559

VX2 [V]

1.682

1.567

1.344

1.567

1.342

VDS,sat1 [mV]

46.845

46.845

46.845

46.845

46.845

VDS,sat2 [mV]

46.845

46.842

46.841

46.845

46.845

Iout [μA]

1.18

2.33

4.55

2.34

4.56

What could be happeining here?

Thanks in advanced!

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Include CDF callback parameters in netlist

August 2, 2018, 1:46 am
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Dear All,

I'm completing a test design using the gpdk045 and gm/ID methodology for educational purpose. For my technology generation (lookup tables of DC sweeps) I use the gm/ID starter kit scripts of Boris Murmann freely available on the net which I have adapted for the gdpk045. This enables quickly looking at design trade-offs in Matlab. However the results of a simple single transistor simulation between Virtuoso & Matlab are different.

This is because the area & perimeter parameters are not included in my netlist, but are included in a Virtuoso simulation. For a difference in netlist see below:

mn       (vdn vgn 0 vbn) g45n1svt  l=length*1e-6 w=5e-6 nf=5  <-- how it is scripted in Matlab netlist generation

NM3    (net09 net09 0 0) g45n1svt w=(5u) l=45n nf=5 as=460f ad=460f ps=6.92u \   <-- How virtuoso simulation netlist looks like
pd=6.92u nrd=18.4m nrs=18.4m sa=140n sb=140n sd=160n sca=72.26287 \
scb=0.06569 scc=0.00861 m=(1)

These CDF parameters: as, ad, ps, pd, nrd, .. are calculated using callback functions which depend on the transistor dimensions. How can I use these callback functions to extend my Matlab netlist so I can achieve accurate lookup tables?

Best regards

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Preventing a stupid schematic mistake with NMOS back-gates

August 2, 2018, 8:13 am
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I have a question that I suspect is more of a pdk thing than a Cadence thing. A regular PMOS symbol in our TSMC 0.18um library has 4 terminals (D, G. S. BG). That's fine. A regular NMOS symbol also has 4 terminals (D, G. S. BG) but that's not so fine because the BG terminal is really the substrate and there's only one place that should (normally) be connected i.e. ground. Having it available as a pin enables trouble because you can connect it to anything. Note that the library also contains isolated deep n-well NMOS devices that do have a valid BG terminal, but I'm focusing on just the regular NMOS for this discussion.

In the attached diagram, I show two NMOS "diode" stacks. The left stack has all the NMOS devices having their BG terminals connected to ground. The right stack has all the NMOS devices with their BG terminals connected to their source terminals. In the real world, the BG terminals in the bad stack would short their source terminals to ground so you'd only end up with one effective diode in that stack (the top one).

Some thoughts: when you do a check and save on the attached circuit you'd hope that you'd get an error for the bad stack (global substrate shorting out multiple different nets), but you don't. When you run a simulation of the circuit in Spectre it works just fine - no warnings or errors and the bad stack produces an accumulating set of Vgs voltages just like the good stack.

We just had a situation where a designer who should have known better used a bad stack and made a perfectly functional circuit that met all specs :-/. Is there a way to catch this at the schematic check and save time? This sort of thing shouldn't be happening in 2018...

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Monte Carlo for Verilog A based model file

August 2, 2018, 10:31 am
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Hi,

I created a symbol using verilogA from 3 file which contains the defination for the other module, I created the following modification in the top level file

module FET(Drain,Gate,Source,Sub);


parameter real n1= 2;
parameter real n2=1;

(*cds_inherited_parameter*) parameter real monten1=0;
(*cds_inherited_parameter*) parameter real monten2=0;

localparam real n1_eff = n1 + monten1;
localparam real n2_eff = n2 + monten2;

FET_L2 #(.Lch(Lch),.Lgeff(Lgeff),.Lss(Lss),.Ldd(Ldd),.Efi(Efi),.Kgate(Kgate),.Tox(Tox),.Csub(Csub),.Ccsd(Ccsd),.CoupleRatio(CoupleRatio),.Vfbn(Vfbn),.Dout(Dout),.Sout(Sout),.GF(min(Wgate/1.0e-12,1.0)),.Pitch(Pitch),.CNTPos(1),.n1(n1_eff),.n2(n2_eff)) XNCNFET_L2_edge (int_Drain1, int_Gate1, int_Source1, Sub, int_Drain1);

and then i created a spectreText of the model and included it in the model library

simulator lang=spectre

subckt NCNFET_L3_MC1 Drain Gate Source Sub
parameters monten1 = 10 monten2 = 10
statistics {
mismatch {
vary monten1 dist=gauss std=5
vary monten2 dist=gauss std=5
}
}
ends NCNFET_L3_MC

but Im getting the following error:-

The HDL cell-view "shobhit" "NCNFET_L3_MC1" "veriloga" does not have view-specific
simulation data. To create the data please open and save the view.
You may also update the view by executing the following SKILL command:
ahdlUpdateViewInfo("shobhit" ?cell "NCNFET_L3_MC1" ?view "veriloga")
End netlisting Aug 2 13:26:14 2018

Im using IC6.7 and mmsim15.10

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