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set parameter in definition files of adexl but given error of variable not defined (monte carlo simulation)

August 2, 2018, 4:32 pm
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I want to vary some resistor/capacitor values in monte carlo simulation and hence write a definition file named mc.h to be included in adexl simulation.

But the adexl will still request me to give values to this parameters.

What's more, my stastictics block are not recognized by monte carlo simulation and hence there is no variation reported in the output. Can anyone tell me what do I do wrong?

I have tried to post twice here but my post was considerred as abusive, I don't understand why. I will post more codes if this post will be posted.

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ADE-XL: possible to change binding of "Open Terminal" button (launch xterm)?

August 3, 2018, 7:38 am
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Hi! I recently switched from IC617 to ICADV12.2 (64b.500.5), and now when I press the "Open Terminal" button in ADE-XL (results tab), two strange things happen:

1) It doesn't open the terminal on the results directory corresponding to the tab from which I click the button. Instead, it takes me to my home folder.

2) It doesn't seem to run the "xterm" command as defined in my .cshrc, where it's aliased to "xterm -rv" to reverse the colors. Instead, it seems to execute a raw 'xterm' command. Since I have my shell colors (prompt, filetypes, etc) configured for a dark background, the opened xterm has very bad contrast and becomes very difficult to use.

In IC617 these problems wouldn't occur: the terminal was opened in the results directories, and it executed xterm as aliased in my .cshrc (thus with the reversed colors).

Is there a way I can change what the "Open Terminal" button executes in ICADV12.2, to modify it to what IC617 was running?

Thanks and regards, Jorge.

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VPS-L: vsaplot can't find "design.info" file

August 6, 2018, 11:18 am
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I'm running VPS-L in batch mode (version IC617isr21).  I can run an EM analysis and get valid text results.  Then I run the "write_em_vsaplot_db" command (it runs without errors) and open "vsaplot" from the command line.  But I am unable to get vsaplot to load a results file -- it always errors out saying it can't find a "design.info" file.  I tried both psf and vavodb output formats.  Any suggestions?  Thanks

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ADE-XL: force re-evaluation of Matlab script edited outside Virtuoso

August 7, 2018, 8:35 am
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Hello! Is there a way to force ADE-XL to re-evaluate Matlab scripts? I always edit my scripts outside Virtuoso, and when I press the re-evaluate button in ADE-XL nothing changes and I get the following message in the CIW:

"INFO (ADEXL-8013): Re-evaluation of the resuts for history 'Interactive.XX' is not required because there is no change in the outputs setup."

So far the only way I found around this is to save the script with a different name, manually changing the script name in ADE-XL, and then re-evaluating, which is cumbersome. I'd like to re-evaluate the script just by pressing the "re-evaluate" button, without needing to change the outputs setup manually... is this possible?

Thanks and regards, Jorge.

P.S. As I store and edit the scripts from a centralized location in my filesystem, I have the following setting in my .cdsenv:

adexl.gui copyMeasurementScripts boolean nil

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Plotting across corners with internal sweep in maestro

August 7, 2018, 2:12 pm
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Hi,

I am running virtuoso 6.1.7 500.17. In my TB, I created a maestro view (my first one) and ran a simulation with the following corners for one test:

CornersTM_1st_internal_sweepTM_2nd_internal_sweep
TM_2nd_internal_sweep_var100**(abs(1-undeuxtroisquatre))
TM_2nd_internal_sweep_var100**(abs(2-undeuxtroisquatre))
TM_2nd_internal_sweep_var100**(abs(3-undeuxtroisquatre))
TM_2nd_internal_sweep_var100**(abs(4-undeuxtroisquatre))
TM_1st_internal_sweep_var10**(abs(1-undeuxtroisquatre))0
TM_1st_internal_sweep_var20**(abs(2-undeuxtroisquatre))0
TM_1st_internal_sweep_var30**(abs(3-undeuxtroisquatre))0
TM_1st_internal_sweep_var40**(abs(4-undeuxtroisquatre))0
undeuxtroisquatre1 2 3 41 2 3 4

However, the RMB over the output tab and neither plot all neither Quick plot all returns the plots of the corner TM_1st_internal_sweep, I only get the plots of the last executed TM_2nd_internal_sweep.

I know that it could be workaround by avoiding undeuxtroisquatre variable and expending all corners,but it is more compact like this and multichannels circuits are easier to design and verify with this kind of setup while keeping a readable corner setup window.

Some time ago, someone found a similar issue in his ocean script. As I don't know much the backend of cadence tools, I am posting here.

Kind regards,

Gabriel

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design kits for a new member in cadence

August 8, 2018, 3:50 am
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Dear Sir/Mme,

I purchased cadence tools since two years and the system as cadence is running (2018) with no design kits no technology and they said it is generic, and I did apply for different technology 0.35, 0.18, 0.13, 90nm, 65 nm, based on the instructions that was provided from Wendy.Fannes@imec.be>, Richard Bishop <richard.bishop@stfc.ac.uk> and I received nothing, so what I am supposed to do to gain access to these design kits, as you know without design kits and technology cadence tools will be something like vehicle with no engine.

this is urgent request as the I am paying for the cadence for two years for nothing.

your help and cooperation to guide me to the right direction is appreciated.

Abdullah

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how to enable to show all the simulation warnings

August 8, 2018, 3:59 pm
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Hi All,

In the transient simulation, there are many warnings, but they are suppressed. Do you know where to turn ON the option to show all the warnings or a much bigger number (say 100 instead 5)? 

Only one connection to the following 20 nodes:

inst_xx.inst_top_core.inst_top_analog.net034
inst_xx.inst_top_core.inst_top_analog.net040
inst_xx.inst_top_core.inst_top_analog.ibp0p8ua_ztc<4>
inst_xx.inst_top_core.inst_top_analog.ibp0p8ua_ztc<3>
inst_xx.inst_top_core.inst_top_analog.ibp0p8ua_ztc<2>
Further occurrences of this notice will be suppressed.

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Checking installation of PDK is correct

August 8, 2018, 4:19 pm
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We are changing manufacturer from MOSIS to Europractice, so I changed my TSMC N65 pdk provided by mosis to the equivalent pdk provided by europractice. Since the installation process has several options, and I am not the one who installed the PDK from Mosis, I want to test the newly installed pdk to make sure it is the SAME as the PDK I use before. I test the pdk by using ADE simulator for the same schematic, and same settings except in model libraries, I change the model files, and simulate for both new pdk model files and the old pdk model files. If I install the same PDK, I expect the simulation results should be the same. However, I find that the simulation results were different.

Since I am still relatively new, I would like to verify if my test for checking if I installed the same pdk valid? I.e. is the only thing that I need to change to compare simulation of the pdks the model libraries? Note, I also ran DRC and LVS on layout after changing pdk, using the new pdk's calibre.drc and calibre.lvs rules, and they are still clean.

Since simulation results are different, my guess now is that I changes some setting in the installation process? Does that seem like a reasonable assumption? I contacted tsmc support about installation, but I would like to verify that my testing of the installed pdk makes sense

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Library Manager: .cdsenv / .cdsinit settings not taking effect

August 8, 2018, 11:32 pm
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Hi! I am trying to enforce some Library Manager settings, but somehow they are not taking effect. For instance, I have added the following lines in my setup files:

-In my .cdsinit:
envSetVal("cdsLibManager.main" "showFilesOn" 'boolean t)
envSetVal("cdsLibManager.main" "showCategoriesOn" 'boolean t)
envSetVal("cdsLibManager.copy" "addToCategoryOn" 'boolean t)
envSetVal("cdsLibManager.copy" "addToCategoryName" 'string "devel")

-In my .cdsenv:
cdsLibManager.main    showFilesOn            boolean        nil
cdsLibManager.main    showCategoriesOn    boolean        t
cdsLibManager.copy    addToCategoryOn        boolean        t
cdsLibManager.copy    addToCategoryName    string        "devel"

...but the is no change in the Library Manager behavior (things stay as default: no categories nor files are shown, and the copy dialog has the "add to category" field disabled and empty).

What can be going wrong?

Thanks and regards, Jorge.

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How do you generate a layout from schematic in Virtuoso IC 6.1.5?

August 9, 2018, 7:38 am
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I know how to generate a layout from schematic in icfb (IC 5.1) using the Tools -> Design Synthesis menu in the Schematics XL window.

Unfortunately this menu does not seem to exist in the newer version of Schematics XL, and I cannot find any explanation on how to do this after searching online (all tutorials I found talk about the old version).

Can anyone help?

Thank you

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fail to use VAR as 'tran' analysis parameter

August 10, 2018, 12:07 am
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Hi All

Virtuoso IC 6.1.7.500.18 is used.

I am using the variable for the stop time of the transient simulation.

Just putting VAR("tSim") in the stop time field.

This method runs pretty well most of time, and all of sudden it does not work, with the error message in the log file as:

Error found by spectre during hierarchy flattening.
ERROR (SFE-1997): "amsControlSpectre.scs" 12: tran: parameter `stop':
Function `VAR' is not defined. Update the netlist to define the
function.

when I open the "amsControlSpectre.scs" file, and comparing it against a working case, I see the difference there:

  • Problematic case

tran tran stop=VAR("tSim") errpreset=conservative outputstart=0 skipdc=no \
write="spectre.ic" writefinal="spectre.fc" method=traponly annotate=status \
maxiters=5

  • Working case

tran tran stop=tSim errpreset=conservative outputstart=0 skipdc=no \
write="spectre.ic" writefinal="spectre.fc" method=traponly annotate=status \
maxiters=5

As the "amsControlSpectre.scs" file is generated automatically, does anyone know why the whole string of stop time setting is parsed?

And how to solve it.

P.S I have experienced this issue many times in the past, usually I created a new empty test, and loaded state, and then the issue is gone.

But this trick does not work this time.

Many thanks in advance.

Best Regards

Yi 

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CDF parameters reusing default value from veriloga

August 10, 2018, 8:11 am
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I have a veriloga model for cell 'mosfet_model', where I declared parameters such as:

parameter real w = 2u;

parameter real l = 0.5u;

Then I create a schematic cell 'inverter' which instanciates a symbol of cell 'mosfet_model' and some other components.

I can edit the parameters w and l in the Object Properties of the instance of cell 'mosfet_model' and by default, they show the same default values as in the veriloga code. But I want to make them editable by parents of the 'inverter' cell.

So I change the properties in the mosfet_model instance as: w = pPar("w") and l = pPar("l").

Then I created symbol for 'inverter' and I can see the w and l parameters in inverter object properties.

So far, so good. But is there a way for 'inverter' to also show the same default values as in the veriloga?

Right now I see blank spaces for every parameter field in inverter object properties, but I would like it to automatically fill up with w = 2u and l = 0.5u that was in the veriloga, just like it does with 'mosfet_model'.

Is that possible? I know I can edit the CDF and add the default values explicitly, but I am worried about making changes in the veriloga that will not reflect on the CDF defaults, so I think it would be preferable to have the two linked together somehow.

EDIT: My tool version is IC 6.1.5

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APS: better Hyperthreading ON or OFF on the machine?

August 10, 2018, 8:22 am
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Hi! We recently got some new servers, and IT asked if they should enable or disable Hyperthreading on them (which effectively doubles the number of cores available for simulation). In the past I've tried APS in servers both and without APS, and it seemed to me that the gain in number of cores available made it totally worth using Hyperthreading, in the context of large sweeps and/or Montecarlo simulations (which we do a lot). However I am unsure how much this penalizes the speed of single-run simulations (using APS).

I found an 8-year old post about this, and I am wondering if since then a clear position has developed on the advantages/disadvantages of using Hyperthreading for APS simulations (in particular, of ADCs). Does anybody have some opinion/experience/information on this?

Thanks and regards,

Jorge.

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Why does renaming a file on Cadence Virtuoso take so much time?

August 11, 2018, 9:32 pm
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Hi,

I have observed that renaming a file (like a cell view name/schematic) takes so much time on Virtuoso takes so much time even if I deselect Update Instances option. On the other hand, if I copy the view and then delete the old view it's really fast. Is this a bug or there is some specific reason behind it? It's frustrating sometimes because I have things running in the background and I can't open them when virtuoso gets stuck due to renaming.

-Venkat

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SDF back annotation in systemVerilog design using interfaces

August 13, 2018, 11:35 am
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I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the modules. here is part of the code:

module topmodule(
intf1   clk,inp1,inp2,outp);

intf1  out();

// Instance the interface with an input, using named connection

 RC DUT(clk, inp1, inp2, out);

and here is part of interface definition,

interface intf1;
logic data=0;

and I have two task and function in my interface. I write a SDF file but modelsim said 'failed to find port '/tbench_top/clk/data' and 'failed to find port '/tbench_top/DUT/inp1/data'. It means it didn't recognize the 'data' port which is defined within the interface. here is part of my SDF file,

INTERCONNECT clk.data DUT.inp1.data (.145::.145) (.125::.125))

So, how must I write SDF when I use interfaces? Thanks for any help.

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I have a problem adding custom vias in IC 6

August 13, 2018, 6:54 pm
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Hi,

I used to do this many times in IC5 and it worked fine, but our company decided to switch to IC 6 for the new projects and I am stuck. The problem is adding the customized vias that are coming with the standard cells IP library (in the lef file) so importing the def file that results from Encounter will find them and instatiate them in the correct places.

In IC5 I used to import the lef file having the standard cells and technology info into a library attached to the main pdk techlib ( we are using TSMC, used 0.18um until now, current project is in 0.11). The import process was adding the abstract views of the standard cells in the library and the technology information into the techlib.

I tried the same thing in IC6. It created the standard cells abstract views ( it is not really important for what I use them for, but I was surprised that the metal1 in the abstract views was imported as METAL1:drawing instead of METAL1:net as in IC5). There was a lot of technology info that was added or modified in the techlib also. But the vias that I was expecting are not showing. I dumped the techlib and they do show up in "customViaDefs" section but, unlike the other vias in that section, the viewname for them is "via", not "symbolic" or "layout". Like this:

(VIA1   tsmc11rf   VIA1    via   METAL1 METAL2  1.02)

If I try to instantiate them manually in a block, they do not show up in any group. If I import the def file with a digital block, they kind of show up ( if I select the area where a via should be I can see something, but the size is zero). I cannot find any info in the Cadence documentation about how this info should be entered. Also, I see some other vias in that section, like via2ts for example, that also have only one line, like:

(via2ts   tsmc11rf  via2ts  symbolic   METAL2  METAL3   1.02)

When I instantiate such a via, it is a cross via with M2 extension on y axis much longer than in the regular cross via ( for minimum metal area if you stack several vias)

I would appreciate if anybody can tell me where is the rest of the info for these vias located because it is definitely not showing up in the dump file. Or how to add the fias from the lef file in the technology.

Thanks a lot 

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Multi-Voltage domain pin checks at schematic level

August 14, 2018, 5:45 am
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Hi all.

I want to exploit the pin properties from the Create Pin Form (signal Type, Supply Sensitivity, and so on) in order to check if my domain and signal are consistent based on the name of the pin among other criteria. 

For example, for all signals with the wild card *dvdd_i or *dvdd_o, the supply definition should be dvdd and the ground definition dvss. Some basic checks are available on Schematic Editor, but I presume that there might exist a tool that check it in a deeper level or can be integrated to the flow.

Any suggestion on how I could do it?

Thanks in advance

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save waveform to file during simulation

August 17, 2018, 10:17 am
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Hi,

I'm trying to find a way to save waveform to a file while sim is running.

I was able to find a few ocean scripts in this forum but I wonder if there's i.e.veriloga script that I can create a cell and put to the testbench since I'm not familiar w. Ocean.

thanks,

Kevin

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probing signal in av_extracted_RC

August 17, 2018, 10:38 am
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Hello,

I'm trying to probe some internal signal nodes of an RC extracted circuit, searching for root cause of a DC  offset.

The simulation is a simple dcOp from ADE-L on a test bench defined by hierarchy editor.

Results-->Print-->DC node voltages  will indeed print the voltage on any node but only as long as that node coincides with a pin.

Any of the other intermediate nodes (separated by presistors)  are selectable and get highlighted but only produce a question mark.

Also the result browser does not get me any further.

I'm sure the simulator computed the all the internal node voltages, but how get them out? 

I tried Outputs-->Save All-->Select signals to output(save)="all" and various settings for "subcktprobelvl"

Also in QRC played with net_name_space = "SCHEMATIC" iso "LAYOUT". Does not make any difference.

Cadence-ic-/06.17.717.

groet

Hans

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verilog-a model help

August 17, 2018, 11:35 am
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Hi,

I am new to verilogA. I am looking for veriloga code that generates a text output whenever gate of any transistor pmos or nmos rises to a file.

Satendra

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