I have done the layout of a cell and included all the pins that were in the schematic by using "generate selected from source" for each one of them and choosing the appropriate pin layer. The "connectivity -> check --> against source" and "connectivity--> update --> components and nets" validates that the pins have bee placed.
DRC with PVS is clean.
Running LVS with PVS results in mismatch showing all pins are missing in layout.
I have an ocean script that runs a transient simulation and then creates a waveform using artListToWaveform() that I want to overlay onto the waveform of interest. Frustratingly, when I plot the two waveforms they always end up in two different subwindows. I can plot any number of waveforms from the simulation into the same subwindow, but the created artListToWaveform() waveform simply won't plot in the same subwindow as the "real" waveforms. The x-axis limits for the generated waveform are the same as the real waveforms. Any ideas?
Hi
I know we can change temperature in one single transient simulation by using the Dynamic Parameter and put "Parameter Name" as temp.
There are two options there: One for Parameter Vector (that we can input the time step and temperature) and I am fine with option.
Another option is to include a parameter file. But I don't know the format for the parameter file. Could anyone show me some examples for this? If you could show me two examples: one for temperature and one for a general parameter (say for voltage levels for a DC source, etc), that would be great.
Thank you very much.
Andrew
Hi,
I've recently been playing around with info balloons in a schematic view. I was wondering, is it possible to display some pertinent text in a balloon when hovering over an instance?
Something like "This amplifier does such-and-such", so that someone else can hover over individual devices or instances and get information on what they're do.
My apologies if there's already something else that does this.
Thanks
Derek
Hi,
In calculator we have a function named "cross" which gives the time at which the respective signal crosses a set value(constant).
if one of the waveform was constant, I would have taken the average value of it and compare the 1st waveform with these average value using cross function.
But what if both the waveforms are random ?
How can i know at what time does the 2 random waveform cross each other? is there any direct function which i can use?
Regards,
Jagdish
I'm trying to make a schematic symbol that looks "functional" instead of looking like yet another box. Is there a way to select a region of the schematic (including wires, instances, labels etc.) and paste it into the symbol with everything visible ending up on the usual layer the symbol is drawn on? I'd use that as a starting point for making a simplified, functional symbol. I did already try doing just the copy and paste into the symbol - all the schematic elements did copy across into the symbol but surprisingly everything retained it's schematic functionality and layers i.e. I could still select instances and change their parameters etc. even though I was in the symbol view!
Hello,
While I was trying to make extraction with QRC tool, I found out that QRC is not installed in our servers. In EXT151 file there are: "Hotfix_EXT15.11.000-Q2_lnx86.sdp", "ic_index.sdx" and "kits" files. I am trying to find a way to install these files. As I found, using installspace is one of the ways. But I couldn't find any suggestion for install the program with hotfix files. In my situation, using hotfix files would be more easy for me. If would you explain or show me a way to do it, it will be so greatfull.
I am working on a script, which needs library & cell list.
Instead of manually parsing cds.lib to get libraries and it's cells. I would like to know,
if there is an existing command, which can give library list and cell list from command-line.
In the property of each component, there are CDF parameter, Value, and Display Options. The default options are "off" always. Is that possible I can change this "off" status to "both" initially ? So this change can be effective afterwards still ?
BR
Hello,
I imported a new library, umc130nm. I also defined it in assure_tech.lib file. While I try to do LVS, I choose these technology. But after I click to Apply/OK, I see this error:
Neirther extracted rules file nor RSF include file name was specified.
As I understand, Assura can not figure out where is my RSF file ( in RSF file I already specified my extract and compare rule files ). I copied RSF file to library for try but it did not work. Also I looked every file in library to fdin something but I could not find anything either. My question is where should I specify my RSF file in my library or Assura.
Thank you
Hello,
After I created my schematic with umc130nm library, I tried to draw layout with Layout XL. When I try to generate all from source ( left bottom button) it put component but after I push " Shift+F" and try to see the layer, on the component it writes ".pcellEvalFailed". Do you have any suggestion to see layers of library component?
Thanks
I found the following thread trying to troubleshoot my problem:
I am trying to do the same thing shown here except I am trying to plot a device in a lower level of the hierarchy. I've created a save.scs file with the following lines:
save I0/Mcp:oppoint
save I0/Mbp:oppoint
I go to Setup -> Model Libraries and add the save.scs file to my global model files. I perform a DC sweep where I am sweeping the length of the device Mcp listed in the save.scs file but I am unable to get Cadence to evaluate the expression getData("I0.Mcp:gm" result 'dc). Cadence says the expression evaluates to nil. I'm running version 6.1.7.
Hi All,
I remember we have an option to select less data point to reduce the simulation file size? For example, the real simulation runs 10 point, but we can configure it to save only one point from the 10 points.
If you happen to remember how to set this up, please let me know.
Thanks.
Andrew
I have declared the tap-cell as STDSUBCONT in CPH, however custom digital placer aborts any attempt to use it with
*WARNING* (VCP-20003): No tap cell masters could be found.
Define tap cells and restart the Custom Digital Placer.
How else am I supposed to declare that cell ?
I have made a verilogams module for a 2 to 4 decoder where both the input and output buses are logic disciplines. I then made a test bench for the module which consisted of a verilog a model of a counter some vpulse sources and it was working.
I was wondering if a verilog ams module can use a vector file as a stimulus with connectlib files selected to determine the logic levels. So far it doesn't seem to be working. Can vec files only work with actual device circuit models or do they work with functional and verilog ams cell views.
I am attaching a picture of the test b
nch with the module and the vector file, so that if I made a mistake, someone here can catch it.
I'm trying to start EMIR analysis by looking at the example that's in:
<MMSIMinstDir>/tools/spectre/examples/EMIR_workshop/mmsim141_emir_workshop/ade_mmsim_voltus_workshop
However, I found that EM/IR Analysis Setup is missing from ADE L menu. Therefore, I can't go further on GUI based EMIR flow.
I've already checked the followings:
1) Successfully I've completed text based EM/IR flow workshop which is in <MMSIMinstDir>/tools/spectre/examples/EMIR_workshop/mmsim141_emir_workshop/textonly_workshop.
Thus, I believe my modification on the environment variable such as MMSIMHOME and CDSHOME is correct.
2) As default, there is a description "setenv MMSIM_ADE_EMIR true" in the file, setup_ade_mmsim_voltus.csh.
It seems that this description is for setting EM/IR Analysis in ADE L to be enable.
Can anyone please help me with this situation?
I'd like to visualize IR drop easily via GUI based EMIR flow rather than text based EMIR flow...
I have 3 ideal interleaving clock signals (zero rise and fall time, no delay) that have no overlaping.
However, after passing through the transition function in verilogA, they overlap each other at rise and fall time durations.
Does anyone have any idea to solve this problem by changing the verilogA code?
y1, y2, y3: 3 ideal interleaving clock signals
V(S4) <+ transition(y1,tdelay,trf);
V(S5) <+ transition(y2,tdelay,trf);
V(S6) <+ transition(y3,tdelay,trf);
Hello,
While I was trying to make an extracted view, QRC gave me the error as below:
Cadence Quantus QRC Extraction - 64-bit Parasitic Extractor - Version
15.1.1-s174 Tue Jul 7 21:42:47 PDT 2015
-------------------------------------------------------------------------------------------------------------------
Copyright 2015 Cadence Design Systems,
Inc.
INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
INFO (LBRCXU-108): Starting
/cds/ASSURA414/tools.lnx86/assura/bin/rcxToDfII /home/nokta/work/cad/LVS6/invLVS/__qrc.rcx_cmd -t -f /home/nokta/work/cad/LVS6/invLVS/extview.tmp -w /home/nokta/work/cad/LVS6/invLVS
WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 27, errno 9 Bad file descriptor
Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.05s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.5-64b:IC6.1.5-64b.500.17 08/31/2015 04:54 (sjfql463) $
sub-version 4.1_USR4_HF25, integ signature 2015-08-28-0751
run on XXX.tr from /cds/ASSURA414/tools.lnx86/assura/bin/64bit/rcxToDfII on Wed Jul 18 19:49:42 2018
Loading tech rule set file : /home/nokta/work/cad/umc13nm/umc13mmrf/techRuleSets
Loading umc13mmrf/libInit.il ...
Loading umc13mmrf/loadCxt.ile ... done!
Loading context 'umc13mmrf' from library 'umc13mmrf' ... done!
Loading context 'pdkUtils' from library 'umc13mmrf' ... done!
Loading context 'Util' from library 'umc13mmrf' ... done!
Loading context 'userUtil' from library 'umc13mmrf' ... done!
Loading context 'oxf_cb' from library 'umc13mmrf' ... done!
Loading umc13mmrf/libInitCustomExit.il ... done!
Loaded umc13mmrf/libInit.il successfully!
*WARNING* No library model for device "RSNWELL".
INFO (LBRCXU-114): Finished /cds/ASSURA414/tools.lnx86/assura/bin/rcxToDfII
INFO (LBRCXU-108): Starting
/cds/ASSURA414/tools.lnx86/assura/bin/avRCXxref /home/nokta/work/cad/LVS6/invLVS/__qrc.rcx_cmd -useRunName
@(#)$CDS: avRCXxref_64 version av4.1:Production:dfII6.1.5-64b:IC6.1.5-64b.500.17 08/31/2015 04:50 (sjfql463) $
sub-version 4.1_USR4_HF25, integ signature 2015-08-28-0751
run on XXX.edu.tr at Wed Jul 18 19:49:43 2018
Reading rsf
INFO (LBRCXU-114): Finished /cds/ASSURA414/tools.lnx86/assura/bin/avRCXxref
INFO (LBRCXM-642): Constructing the RCX run script
/cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen: error while loading shared libraries: libtermcap.so.2: cannot open shared object file: No such file or directory
INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
/cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen -techdir /home/nokta/work/cad/umc13nm/umc13mmrf/LPE -lvs /home/nokta/work/cad/LVS6/invLVS.xcn -p2lvs /home/nokta/work/cad/umc13nm/umc13mmrf/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C,MMCBP_C,MMCTP_C -res_blocking RFSYMBOL,ply,ME1,ME2,ME3,ME4,ME5,ME6,ME7,ME8,MMCBP,MMCTP -p PLY_C,Allgates,PSD_C -cap_unit 1 -blocking CMMC,MMCBP_C,MMCTP_C -blocking MOMVP1_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP1_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C /home/nokta/work/cad/LVS6/invLVS
Forking: /cds/EXT151/tools.lnx86/extraction/bin/64bit//capgen -techdir /home/nokta/work/cad/umc13nm/umc13mmrf/LPE -lvs /home/nokta/work/cad/LVS6/invLVS.xcn -p2lvs /home/nokta/work/cad/umc13nm/umc13mmrf/LPE/p2lvsfile -reseqn -sw3d -length_units meters -blocking RFSYMBOL,DIFF_diel,PSD_C,PLY_C,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C,MMCBP_C,MMCTP_C -res_blocking RFSYMBOL,ply,ME1,ME2,ME3,ME4,ME5,ME6,ME7,ME8,MMCBP,MMCTP -p PLY_C,Allgates,PSD_C -cap_unit 1 -blocking CMMC,MMCBP_C,MMCTP_C -blocking MOMVP1_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP1_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOMVP2_MM_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_SY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_WEL,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C -blocking MOM_MESH_ASY_PSUB,ME1_C,ME2_C,ME3_C,ME4_C,ME5_C,ME6_C,ME7_C,ME8_C /home/nokta/work/cad/LVS6/invLVS
ERROR (LBRCXM-644): Bad return status from RCX script generator. 0x100
INFO (LBRCXM-709): ***** Quantus QRC terminated abnormally *****
Also, I checked CIW but there was no addtional error. Do you have any suggestion about it?
Is there a way to uncheck the Update Instances box in Rename Cell dialog by default (eg. in .cdsinit)?
While placing more than a single flight wire on a terminal in layout, moving the instance will cause the flight lines to remain in the same place, but the connected terminal will create a wire going back to the original location. If doing this with a single flight wire, this is not the case and the flight wire will follow the terminal. Is there a way to have multiple flight wires do the same thing as a single flight wire?