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Title Block strings

June 19, 2018, 1:52 am
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Hello everyone

I have some questions regarding title blocks in Cadence Virtuoso. Unfortunately my research has not yielded any results so far.

I am currently making my own Title Block / sheet border with various information such as designer, date and the like.
To do so I refer to "special strings" such as [@Revision], [@Process] and the like. First of all I'd like to know what we call these "special strings"? I have figured how to handle strings such as @ENG, @Description and @Revision by going to edit->Sheet title. 
But how do I change the strings like @Date, @HitKit and @Process?

I would also like to know, where I can find other available "special strings" like @SheetNumber @SheetTotal or @ApprovedBy.
In general I lack the understanding of how Cadence Virtuoso deals with these specifics of engineering and documentation.

I hope my question is clear. If not I would love to elaborate or provide screenshots/other documentation.

Best regards Jacob

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why in ADE XL monte carlo simulation, the default number of runs is set as 200 ?

June 20, 2018, 2:06 am
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Can anyone explain how the number of runs influence the results?

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VPWLF source in Cadence Virtuoso

June 21, 2018, 4:42 am
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Hi,

I want to give a voltage ramp signal for a circuit. I am using Vpwlf instant available in analogLib.

This works fine if i have same file for all the corners.

But I want to run the simulation at different corners and a specific voltage ramp file for that respective corner, meaning for each corner the file is different.

How can i define the file path in vpwlf as a VARIABLE and then define complete file name in corner setup window????

Regards,

Jagdish

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Transient PLL spur simulation setup

June 23, 2018, 5:55 pm
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Hi, Officers, 

I have a question on how to accurate estimate the spur at PLL output by using transient simulation with DFT function in SpectreRF. 

For example, if the spur is located at 100 kHz offset from the PLL output with the power (or variation) of 1 ps, what would be proper 

setup for time step in transient simulation ? 

Do we need to set the time step to be smaller than 1 ps to extract this spur accurately in the simulation ? 

Sincerely, 

Ruixin 

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Tests/Expressions/Plotting

June 25, 2018, 2:13 am
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Dear Cadence Experts:

I have two questions regarding Tests/Expressions/Plotting in ADE-XL.

I am using ADE-XL from virtuoso version IC6.1.7-64b.500.14. In my test bench I have a number of tests each dealing with a different transistor. The test names distinguish between the tests/transistors. Hence, I am NOT using different names for expressions. I use the same expression name (which possibly refers to other expression names). For example I have test_tr1 and test_tr2 and both have expressions like noise_corner or noise_ids. 

My questions are as below:

1) If an expression form a test (say noise_corner from test_tr1) refers to another expression (say noise_ids), which noise_ids (from which test) will be used? I want obviously noise_ids from test_tr1 to be used in noise_corner from test_tr1 and noise_ids from test_tr2 to be used in noise_corner from test_tr2. Is ADE-XL smart enough to do proper selection of expressions with same name under different test names?

2) If answer to 1) is Yes, why is that when I click on noise_corner and plot it, I don't see test_names in the legend? I see noise_corner for different tests but the viva plot window does not show test names. So it is not possible to know which point is coming from which tests. I tried also to use test names as an axis but it is just not available.

Thanks in advance for your answer/clarification.

Br, 

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Stability Analysis (stb) OTA for active RC integrators

June 26, 2018, 12:02 pm
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Hello,

I am designing a CT sigma-delta modulator with active-RC integrators. I have designed my OTAs and performed manual analysis and compensation of the CMFB loop (I could perform correctly the stb analysis).

However, I would like to use the stb analysis to check it. Most tutorials I have verified on the internet uses stb analysis for operational amplifiers with resistor feedback instead of capacitive feedback.

In my case, I have a fully-differential OTA, and I am using the diffstbprobe. Let's consider my first active RC integrator. It has an input resistor of Rin=100kohm and an 8 pF capacitor. The load of its integrator is another active RC integrator with R=500kohms and C=1 pF. Thus, the load of my first active RC integrator is 500 kohms||8 pF.

I have performed the AC analysis (open loop) with a load of 500 kohms||8 pF and found: DC gain of 43 dB, GBW of 13 MHz and PM of 89 degrees.

For stb analysis, I have followed the tutorial: "Loop Stability Analysis: Differential Opamp Simulation" from Vishal Saxena & Zhu Kehan. However, instead of a feedback resistor I used an 8 pF capacitor, and a load composed by a 500 kOhms resistor. Also, the input resistor of the active RC integrator is equal to Rin.

The results of stb simulations for the differential gain are attached. It seems the TF of high-pass filter. Please, can someone give me some tips on what I am doing wrong?

Should I use the stb analysis for circuits with feedback capacitors?

Kind regards.

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Convergence problem

June 27, 2018, 1:03 pm
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Hi,

Im trying to simulate a circuit but its showing me  convergence error and bad pivot, so I checked yes for the dc_pivot _check (simulation-> options-> analog)  but the error still persist.

Also, I found a spice file which may solve the convergence problem, how can I add it to the spectre simulation

Im using IC6.17 and mmsim15.10.801

thank you

Regards

shobhit

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transient simulation accuracy

June 27, 2018, 1:48 pm
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Hi, 

I am using an ideal delay cell in analoglib. With defined 1 ps delay, the cell is sometimes behaving abnormally with changed slopes. The smaller time strobe and max time step may solve this problem. 

Is this error an systematic offset in the simulation or it would change with the simulation state ? And is this cell similar to the real CMOS transistor, which means that in the transient simulation, the  transistors may appear same artifacts in the simulation ?  And what would be a correct time strobe set for 1 ps delay ? 

Thanks. 

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ADE Distributed Job Name History

June 28, 2018, 6:32 am
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Running Virtuoso version ICADV 12.3-64b.500.19

Submitting jobs in ADE with the Distributed Processing option Job Submit form.

The first field is 'Job Name', it automatically started at job001 and increments every time.

My question is: The form will not ever let you reuse a job name, even if you ran that job months ago and the results are long gone.

I searched in local and home .cadence directories but could not find where this job name history is being stored. How do I reset it so I can 

start over? Thanks!

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Check if a library exists in cds.lib or included cds.lib files from terminal

July 2, 2018, 2:36 am
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Hi,

Is there any cadence utility to check if a library is defined in cds.lib or any included files? I wish to use the utility from terminal.

Thanks,
Bala

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Assura Default License

July 2, 2018, 10:41 pm
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Hello:

I run Assura LVS and it returns a license error:  

Run 'lic_error LMF-02012' for more information.
Failed to obtain license for "Assura_LVS".
Checking out license for Phys_Ver_Sys_LVS_XL

LVS ultimately does run after several minutes with trying a different license: "Phys_Ver_Sys_LVS_XL".  Is there a way to tell Assura to use this license first by default?

Assura (R) Physical Verification Version av4.1:Production:dfII6.1.6-64b:IC6.1.6-64b.500.14

Release 4.1_USR5_HF14

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Max point number in local optimization

July 3, 2018, 6:24 am
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Hi,

When I do a local optimization in virtuoso, it simulates only 11 points but I configured much more options in my variables. I would like to increase this number but I didn't find any option. Could you help me please?

Best regards,

Emmanuel

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custom cap cell from tsmc 0.18um process

July 3, 2018, 3:53 pm
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hello exports,

very dumb question, how should I customize a new cap cell so that I can build my circuits upon? I know I'll need cell symbol, layout, and DRC checked. how should the parasitics be extracted for various PVT corners? would it be possible to make it pcell? any comments or suggestions or points to tutorials will be greatly appreciated.

thanks,

David

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Extracting Noise Plots of Isolated Devices using Single Simulation

July 4, 2018, 6:25 am
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Hello,

I created a small test bench with two transistors. The two transistors are completely isolated from each other. In the noise simulation setup, I am forced to define an output node. If I define the output of one transistor, I am not be able to see the noise plot of the second transistor. This doesn't make sense because I expect the noise parameters (especially flicker) to be dependent on technology or DC parameters.

I am extracting the noise plots using vn in calculator. Is there a way I can get the noise plots for both transistors with a single noise simulation?

Best regards,
Karam

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Plot transient OP vs. Time

July 4, 2018, 7:15 am
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Hi,

I want to plot the transient operating point of a device versus time (e.g device Msrowin, operating point for ids).

One way to achieve this is to create a file "tran_op.scs" and include it with the model files. The file content will be:

             save Mswroin:ids

In the output definitions I would add:  getData("Mswroin:ids" ?result 'tran), then I can plot the "ids" versus time.

Questions:

1) How should the file syntax look like, when the device is in a subcircuit (e.g "/DUT/Mswroin" does not work) ?

2) Is there another (easier) way to evaluate the transient operating point vs. time ?

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ADE Assembler sweep config views problem

July 5, 2018, 1:31 am
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Hi,

I have a simulation setup in ADE Assembler including a sweep of configs of a sub-module (like expained here: community.cadence.com/.../sweeping-multiple-config-views).
Let's say I have a config_a and a config_b for two different versions of a sub-module.
The config of my tests includes config_a as default.

In one test, I save the DC Operating Point together with some other outputs.
After the simulation, I can right-click on any output of this test, and then select Annotate -> DC Node Voltage.

The problem is, that the annotation only works for the default config (config_a), but not for the sweeped config (config_b).
If I try to annotate the DC Node Voltage for the sweep of config_b, the schematic of config_a is opened instead of the schematic of config_b.
Same for right-click-Direct Plot>-..., Print->...

Question:
Is it possible to use Annotate / Direct Plot / ... for sweeped config views in ADE Assembler after simulation?

Info:
Cadence IC6.1.7-500.15

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dump for particular hierarchy.

July 6, 2018, 4:28 am
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Hi ,

we have top file , top file having so many hierarchies after running simulation  will get the dump for total top file.

what i need is , out of so many hierarchies i need the dump for particular hierarchy.

can you please help me out ,how to get the dump for particular hierarchy.

Here we used the commands can you look at once.

Regards,

Mani P V

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Gravity Snapping in IC 6.1.7

July 6, 2018, 2:28 pm
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Hello,

How can I enable gravity snapping to center of objects/layers in Cadence Virtuoso Layout? This was previously available as a check box in the Layout Editor Options.

Thanks.

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Extract schematic from layout or verilog code

July 8, 2018, 11:42 pm
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Hello,

I am a full-custom analog designer but for my project I had to design a semi-custom part. I want to do an overall LVS but I cannot make netlist. I read a lot of article and web sites to do it but it is not clear at all. My technology is UMC180nm. The standard cell are provided by Faraday and they only provides layout (not only a symbol). So I cannot make any schematics from verilog. I also tried to make a netlist from layout to make a schematic afterwards but this also did not work. Can you please help me on this issue. My deadline is very close and I do not know how to do this.

Thank you so much in advance,

Best regards,

Reza

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Accessing ADE XL global variables from within systemverilog block

July 10, 2018, 6:47 am
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Using ADE XL.  I've got a Spectre DUT and am using systemverilog to generate my testbench stimuli. 

I need to access global variables from within the SV testbench so that I can uniquify result filenames. 

How can I do this?  Thank you. 

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