Does this mentioned in ade-xl documentation or somewhere? I appreciate if someone can tell me.

I have two schematics in the same ADE-XL and have their own tests. But their nets name are all same. When I try to use calculator to plot a waveform in one schematic, it only shows VT("X"), how can I know which schematic it refer to. 

Also, when I have one test in ADE-XL, I always use the Results tabs to compare with my previous simulation, sometime I am also confused which results are fetched for calculator expression, since I cannot tell the results are for current simulation or previous simulation.

Regards

Gaofeng

In GUI, there is a trigger like below:

And how do I trigger it via env var? There is "vicCheckPinOrder", but it looks like the superset -- "Check Pin Order".

I am using IC6.1.7.is12.

Thanks

Fred

Dear Cadence experts:

If there a way to sort ADE-XL Results tab data (rows) across multiple columns? Currently, when I click on a column title (e.g. Test or Output), only data for that column are sorted. How can I select for example two columns (say both Test and Output) and sort data (rows) across the two columns? This feature is readily available for example in Excel. 

I am using virtuoso version IC6.1.7-64b.500.14

If this is not possible, is there a way to somehow group or organize the Results (or Output Setup) expressions? Because without any sorting or grouping, things go very hard to manage when you have say 50 to 100 expressions. 

Regards,

I'm simulating a receiver across corners.  Each corner has a different amount of delay.  When I plot a node "across corners" and then generate the resulting eye diagram, all these different delays from the different corners result in the composite eye being much narrower than is the case if the corner delays could be nulled.  What would be the simplest/quickest way I could shift the different corners to into time alignment?  If that can be done, then I can use eyeAppeture to generated stats on the eye at all the nodes along the receive path.  This doesn't have to be automated; it would be fine if I could manually add a shift to each corner.  But once this is done, I would like to be able to save this result to be used by eyeAppeture on different nodes in Assembler.  Thanks in advance.

I have 2 questions about instantiating multiple instances, the multiplier parameter and bus naming conventions in the Schematic editor. If I want to connect 4 MOSFETs( in parallel), in series, with another set of parallel MOSFETs like in figure A, do I do it using figure B or figure C. (I think it is figure B). If I do instantiate four MOSFETs like in figure 3, for both the top and bottom set, and if I make the connecting net a bus of width 4 bits then I think I get figure D.

1)So if I have this right figure A and B are the same, D and C are the same. Is this wrong? 

2) if i want to declare an array of say 128 identical series resistors, how do I go about it? 

Do I have to make the nets on either side a bus of 128 bits and instantiate resistors with R<127:0>? How do I go about declaring an array of identical parallel resistors? I am guessing for a parallel array I don't make the nets on either side of the R<127:0> into 128 bit buses. 

Hi,

Since today I have a strange behaviour in the ADE Explorer. I perform different simulations in order to get some specifications for a fully differential opamp which I designed. All these simulations worked fine until today.

I changed something in the schematic of the opamp and since then the noise simulation is wrong when I simulate only one corner or perform a Monte Carlo simulation. If I simulate multiple corners the noise simulations calculates a correct result.

EG. I simulate for example the Nominal Corner, the noise simulation gives me a result of around 50uV/sqrt(Hz) (at a frequency of 200kHz) (way too much).
If i simulate the nomial corner and for example a corner with a different ambient temperature, the reported noise is around 10nV/sqrt(hz) (in the range of the expected value).

If I then open a debug environment and simulate the noise there it is again around 50uV/sqrt(Hz) (for the nominal corner and also for the other corners).

I tried to revert my opamp schematic to the point where it worked but the strange behaviour stays.

Do you have any ideas what is happening here and how to resolve this issue?

Kind regards

Lukas

Hi all.

I'm simulating a voltage reference temperature behavior using DC Sweep and I'm experiencing a discontinuity on the first derivative for ptat voltage in the first point, it means for -40C to the next temp step. When I check the slope, it looks very linear and smooth.

I'm just asking about the origin of the problem: Could it be a deriv() operator or convergence problem?

Some collegues have also reported this problem. 

Thanks!

For one of  my transient simulations I need to change a set of dynamic parameters at a certain point in time to the design variable corresponding design variables. The simunlator allows me to do this if I select the "parameter" option under "dynamic parameter" in the tran setup menu, but not for the "parameter set". For example, if I need to change the temperature after 2us in my simulation, if I check the "dynamic parameter" option in the tran menu and select "Parameter" and then "temp" from the drop down menu, it lets me input the values in a table in a vector format and I can set the temp value to the global parameter "temp" at 2us and it works and the simulations runs fine.

But, if I try to select "parameter set' to do the same thing with more than one variable as shown below:

I get the following error:

"Unexpected open square bracket "[". Expected end of file or end of line. Cannot run the simulation because of syntax error. Correct the error and rerun the simulation."

The tran setup in "input.scs" looks like the following:

tran tran stop=5u errpreset=conservative paramset=paramSet1 \
    write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5
 paramSet1 paramset {
time  temp  vdd
0    27    3.3
2u    temp    vdd
}

I am guessing that I need to put the dynamic variable in the parameter set in a certain syntax. Can someone please help me with this?

Thank you!

hi,

i wrote one file which contents is "save *:all" and simulate the dc analysis, all the mosfet dc parameters have been saved, i set the outputs expression and for example, getData("NM0:ids"? result "dc"), i want to plot the current ids from matlab, then i open matlab from toobar, i can got the adeInfo in the workspace, how to plot output expression like this? thanks a lot.

Hello,

I'm looking for help in porting a design from one technology to another (both fairly similar 180nm CMOS) and I already have routines to translate schematics and match up corresponding pCells. However, I'd like to know if the same thing can be done for a layout. Is there any information out there for translating a finished design into a new technology and keeping the connectivity and pCell information for the layout as well as the schematic?

I'd found this post from six years ago but I can't get to the COS solution mentioned and the discussion just sort of peters out.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/23001/translating-existing-cells-into-a-different-technology#

Is what I am trying to do not realistic or are there some basic elements that already exist that could help me.

Thanks for the help if anyone has any suggestions.

Matthew Cordrey-Gale

Hello,

Could you please layout the details, how to simulate a fully differential output buffer(Tx) and fully differential input buffer(Rx) ibis model in Virtuoso?!

The ibis buffer from analogLib is not working in differential mode. Beside there are no options to specify the io signal type (e.g. if the signal io is P/N type). Also I could not specify the Pin number!

Only the Model name is not sufficient in my case. I wish to declare the pin number and type of signal along with the model name such that the io buffer could identify the target model distinctly within the XXX.ibs file. Kindly give your suggestion ASAP.

Regards,

Bitan
Virtuoso Version: 6.1.6-64b

Simulator: Specter

Hello,

I have an integrator circuit that is reset periodically. Right before the reset, a sample is taken on which I would like to calculate the noise.

Conceptually, after the reset, the system is not in steady state and the output (noise) variance will grow until the system reaches steady-state.

The noise analysis gives me the steady state result. The output noise is attached at the end and the total integrated noise is 125uVrms.

Now I run pss+pnoise with tdnoise and plot the total integrated noise vs. time. This is what the outcome looks like:

Except for the y-axis scaling exactly as expected! The waveform of the reset signal is clearly visible: The system is reset between about 0 and 70ns, then the integrator starts and the total noise increases. It reaches a maximum at 250ns=0ns; then it is reset again.

However, this shows the plot for different values of "Integration Stop Frequency". 4MHz, 1PHz, 10PHz, 100PHz, 1000PHz:

Dependening on which value I choose for the stop frequency I can make the total noise shift arbitrarily. This does not make sense to me. For noise it's clearly visible that the system is bandlimited so the total noise must converge to a fixed number. Furthermore, it must be always smaller than the value in steady state (125uVrms from .noise). Particularly, when I make the number of sidebands (and maxacfreq in pss) very high, the number must converge to the one from .noise.

Why is this? Are my settings wrong?

I use pss; beat freq=4MHz, number harmonics=49, moderate, maxacfreq=1G

pnoise: Start: 1, Stop: 100G (some very high number), 10pts per decade. Maximum sidebands: 51.

Finally I use ADE L -> Direct Plot -> tdnoise -> Integ Output Noise, Total Noise, Start Frequency 1 Hz and Stop Frequency I vary from 1 MHz .... 10000PHz with difference results (as above).

As can be inferred from the plots, the control signals run at 4 MHz with ~21:6 duty cycle.

PS: This is the .noise output. Total integrated: 125uVrms.

Hi Everyone,

I would like to run a command line spectre simulation with an ocean script as postprocessing. My problem is that I can not access the two ac simulation results in the inner loop of the sweep. I would like to get a waveform family to work with. I have done parametric sweep in the past couple of times, but not in the recent years, and I am not sure I used two analysis of the same type inside the sweep loop. I would expect that a sweep analysis will not alter the analysis names, just it would add multiple waveforms for a signals.

My simulation statements in my netlist:

sw_vg sweep param=VGS start=0.1 stop=0.6 step=0.05 {
   dcOp dc
   dcOpInfo info what=oppoint where=rawfile
   // AC source @ VG
   ac_g ac start=1M stop=1T
   alt_gac0 alter param=VAC_G value=0
   alt_dac1 alter param=VAC_D value=1
   // AC source @ VD
  ac_d ac start=1M stop=1T
}

My OCEAN output:

ocean> results()
ocean> (dcOp dcOpInfo ac "sw_vg_ac_d-sweep" model
instance output designParamVals primitives subckts
)

I would like to access the two AC simulations as "ac_g-ac" and "ac_d-ac", just as in the case without the sweep analysis, to make the script more general and easier to read and make it future proof - maybe the AC simulation statement changes and the postprocessing commands for the old AC analysis would give misleading results.

Seemingly there are two AC analysis in the result() output, but all waveforms are the same except one if I plot them - checked with ' plot(i("VD_AC:p" ?result "sw_vg_ac_d-sweep") - i("VD_AC:p" ?result "ac")) ', so I am pretty sure that I make something wrong, but I was not able to figure out what it is. I want to see/access all waveforms in both AC simulation. How am I supposed to do that?

Regards,
Zoltan

MMSIM Version: 15.1.0.627.isr12
Cadence/OCEAN Version: ICADV12.2-64b.500.7

Hello, 

I am seeking help to know if there is a built-in function in the Cadence calculator which accomplishes what I need. I have to signals 1 and 2. The first signal is a square pulse and the second signal is a ramp. I need to know the x value when signal 1 crosses a certain threshold. I know I can do this using the cross function. At the same x value I need to know the corresponding y value on signal 2. Is there a way to do this using calculator functions or building your own expression incorporating the "cross" function?

Thanks 

Hello,

I'm using deepprobe in my simulation, but when replace the schematic view with analog extract it's stops working.

For sim with schematic I use such syntax for access some net 
top_level.level1.level0.net_name 

In analog extract no hierarchy, and the same net is renamed to

level1|level0|net_name

 I've put in the deeprobe properties

top_level.level1|level0|net_name 

But simulation can't start because of the error " Unexpected operator "|"

What syntax should I use in this case?

Regards,

Nikolay

I am trying to find any documentation on the expected xml syntax for an sdb file to be loaded for corner setup.   Maybe a list of the expected keywords and/or values.  Examples might be good but I have a few already that do not help as they are very simple ones.

Regards

Joe

I have a a somewhat large circuit with an inductor. I don't set any initial condition for inductor current but from the simulation result its current is very large about 142A at the begining of the waveform. 

Here is the output log file and netlist file:

Notice from spectre during topology check.
Only one connection to node `maxe'.

Circuit inventory:
nodes 28
adder 2
capacitor 3
error_controller 1
inductor 1
myComp 1
pi_controller 1
relay 4
resistor 8
soft_voltage_clamp 1
vcvs 3
vsource 7

Time for parsing: CPU = 2.999 ms, elapsed = 6.71411 ms.
Time accumulated: CPU = 185.971 ms, elapsed = 183.428 ms.
Peak resident memory used = 29.2 Mbytes.

Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre0_16925_15, ).

Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.

***********************************************
Transient Analysis `tran': time = (0 s -> 5 ms)
***********************************************
DC simulation time: CPU = 2 ms, elapsed = 1.28007 ms.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 5 ms
step = 5 us
maxstep = 100 us
ic = all
useprevic = no
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 1 pF
gmin = 1 pS

tran: time = 125 us (2.5 %), step = 2.453 ns (49.1 u%)
tran: time = 375 us (7.5 %), step = 1.541 ns (30.8 u%)
tran: time = 625 us (12.5 %), step = 1.541 ns (30.8 u%)
tran: time = 875 us (17.5 %), step = 1.547 ns (30.9 u%)
tran: time = 1.125 ms (22.5 %), step = 1.541 ns (30.8 u%)
tran: time = 1.375 ms (27.5 %), step = 10.5 ps (210 n%)
tran: time = 1.625 ms (32.5 %), step = 10.5 ps (210 n%)
tran: time = 1.875 ms (37.5 %), step = 1.547 ns (30.9 u%)
tran: time = 2.125 ms (42.5 %), step = 1.541 ns (30.8 u%)
tran: time = 2.375 ms (47.5 %), step = 1.546 ns (30.9 u%)
tran: time = 2.625 ms (52.5 %), step = 1.546 ns (30.9 u%)
tran: time = 2.875 ms (57.5 %), step = 1.541 ns (30.8 u%)
tran: time = 3.125 ms (62.5 %), step = 1.547 ns (30.9 u%)
tran: time = 3.375 ms (67.5 %), step = 10.5 ps (210 n%)
tran: time = 3.625 ms (72.5 %), step = 1.546 ns (30.9 u%)
tran: time = 3.875 ms (77.5 %), step = 1.541 ns (30.8 u%)
tran: time = 4.125 ms (82.5 %), step = 1.546 ns (30.9 u%)
tran: time = 4.375 ms (87.5 %), step = 10.5 ps (210 n%)
tran: time = 4.625 ms (92.5 %), step = 1.546 ns (30.9 u%)
tran: time = 4.875 ms (97.5 %), step = 1.541 ns (30.8 u%)
Number of accepted tran steps = 429252

Notice from spectre during transient analysis `tran'.
Trapezoidal ringing is detected during tran analysis.
Please use method=trap for better results and performance.

Initial condition solution time: CPU = 2 ms, elapsed = 1.33395 ms.
Intrinsic tran analysis time: CPU = 43.2364 s, elapsed = 43.2487 s.
Total time required for tran analysis `tran': CPU = 43.2404 s, elapsed = 43.2533 s.
Time accumulated: CPU = 46.187 s, elapsed = 47.8582 s.
Peak resident memory used = 319 Mbytes.

finalTimeOP: writing operating point information to rawfile.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.

This is the netlist:

// Generated for: spectre
// Generated on: Jun 14 14:57:00 2018
// Design library name: SIMO
// Design cell name: SIMO_boost
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: SIMO
// Cell name: SIMO_boost
// View name: schematic
V0 (net1 0) vsource dc=3 type=dc
V13 (vdd 0) vsource dc=1 type=dc
V12 (vref3 0) vsource dc=6 type=dc
V11 (vref1 0) vsource dc=4 type=dc
V10 (vref2 0) vsource dc=5 type=dc
V14 (clk 0) vsource type=pulse val0=0 val1=1 period=1u width=100.0n
V1 (vramp 0) vsource type=pwl pwlperiod=1u wave=[ 0 0 990n 1 1u 0 ]
I3 (vclamp vramp S1 vdd 0) myComp tdelay=0 trf=1e-12
I48 (ve2 ve1 net36) adder k1=1 k2=1
I45 (ve3 net36 pi_int) adder k1=1 k2=1
I46 (pi_out vclamp 0) soft_voltage_clamp vclamp_upper=0.8 vclamp_lower=0
I47 (pi_int pi_out) pi_controller kp=10000 ki=1
C8 (net21 0) capacitor c=10u
C7 (net28 0) capacitor c=10u
C6 (net27 0) capacitor c=10u
I2 (ve1 ve2 ve3 clk S1 s4 s5 s6 vdd 0 maxe p n) error_controller \
tdelay=1e-12 trf=1e-12 vth=0.01
R10 (Vo3 net21) resistor r=10m
R0 (Vo3 0) resistor r=20
R9 (p n) resistor r=10m
R8 (Vo2 net28) resistor r=10m
R1 (Vo2 0) resistor r=16.67
R3 (net1 net017) resistor r=10m
R7 (Vo1 net27) resistor r=10m
R2 (Vo1 0) resistor r=13.33
E7 (ve3 0 vref3 Vo3) vcvs gain=1
E5 (ve2 0 vref2 Vo2) vcvs gain=1
E3 (ve1 0 vref1 Vo1) vcvs gain=1
W14 (n Vo3 s6 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W13 (n Vo2 s5 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W0 (n 0 S1 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
W9 (n Vo1 s4 0) relay vt1=400m vt2=600m ropen=1T rclosed=1m
L2 (net017 p) inductor l=4.7u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=5m cmin=1p write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save L2:1 I2:p I2:n W13:1 W9:1 W14:1 W0:1 W9:1 W9:1 W9:1 R7:1 R2:1
saveOptions options save=allpub
ahdl_include "/home3/Huan/Process/MS018/Project/SIMO/myComp/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/adder/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/soft_voltage_clamp/veriloga/veriloga.va"
ahdl_include "/home3/tool/IC616/tools/dfII/samples/artist/ahdlLib/pi_controller/veriloga/veriloga.va"
ahdl_include "/home3/Huan/Process/MS018/Project/SIMO/error_controller_boost_SIMO/veriloga/veriloga.va"

I would like to check the integer output of a decoder matches the integer value i set using the busset instance that drives the decoder.

ive tried using awvDigital2Analog() and numConv() but just cant get it to work.

Is there a function to convert the bus vector to a string or simply an easy way to achieve the above ?

Thanks 

Faisal

Hi,

I'm currently on ICADV12.3-64b and I'm looking for a way to generate a gds file such that the instance names for Pcells(or any other cells that do not have unique names) are the same(e.g suffix is a counter which counts up for every instance encountered) each time I strmout  a gds.

So far, I've tried options such as "flatten PCells" and  "flatten Vias" when exporting the gds, but the results of the fastxor run do not seem to match the fastxor run where I select "create gdsii"(let fastxor create the two gds's).

I need this so that I can run fastxor on a list of cells that exist in multiple libraries through the command line.

Thanks.

After I get my layout from SoC Ecnounter, I wanna import it in Cadence Virtuoso to run Calibre DRC, LVS, PEX and so on. So firstly I import my std cell library (I use Nangate 45nm) then I import the Stram (my gds file) and write the library name (NangateOpenCellLibrary) and attach ASCII Tech File (technology.tf) then I hit translate.  

When I go to the library to open the layout, I face this message; [There are 209 undefined packets found. Most likely, the display resource file (display.drf) for a library was not merged. To merge a display.drf file use CIW ->Tools->Display->Resource Manager->Merge Command].

What should I merge that (display.drf) with?