I could not read in a spice netlist into cadence and generate a schematic. The spice net list is created by Calibre LVS tool.
Cadence GNU popup and tells me it created a log file a a workarea, but there is no spicein.log file.
Can I get some help on this?
Thanks
In Virtuoso Layout XL->Extract layout, what is the function of the Scope setting "Current Cellview and Cellviews in Hierarchy", and of the "Save Extracted Cellviews" button? Does that Scope setting "flatten" those selected cells in memory before running extract?
I would like a way to extract a few cells in the hierachy, which typically contain just custom wires, without having to use the option "Extract connectivity to level" greater than 0, which slows down the extraction; does the Scope setting "Current Cellview and Cellviews in Hierarchy" do that?
Hello,
I am using Safe-Operating-Area or in Cadence language "assert checks" files in an analog Virtuoso flow. I'd like to be able to program the "duration" parameter in my SOA file from within the Virtuoso envionment. I'm not sure if this is possible and haven't found any threads that really help me up to now.
The files are just included in the "setup->model libraries" section of the ADE environment and contain variables definitions like
"parameters duration=10ns"
If anyone has any pointers to get me started I'd appreciate it.
Many thanks,
Matthew Cordrey-Gale
I am using parametric analysis to plot the curve Vout with time for different Vth values. The plot is in the figure below. The X axis is time, Y axis is voltage Vout. From the graph result, if I put a vertical marker at the point where the circuit reaches steady state period, then on the left (in red circle) you can see two columns V1 and Vth which is sample of Vout with different Vth at this particular time.
From this I would like to plot the curve Vout vs Vth. Is there an easy way to do that?
Also how to copy the two columns into Excel so I can plot it by Excel if we can't plot it by Cadence tool?
I know that I can retype the two columns into Excel one by one and then plot but that would be too slow and take a lot of time. So I am searching an efficient method than that.
Thanks.
I have DesignSync managed layouts in my library. I need to get an oa object corresponding to an older version of the layout. For example in my workspace I have layout/layout.oa for current version. I need to have a layout_v1.1/layout.oa for the older version of the layout.
I need to do this without populating or checking out the older version of the layout, so as to not disturb the version history of the cell or the time stamps.
Is there any SKILL procedure that can handle access to older versions in Synchronicity?
Hello,
Long time ago I was successfully able to disable Flicker noise using "noiseoff_type=[flicker]". This was shown in the last postings of
community.cadence.com/.../referencing-a-model-not-a-model-instance
and made me very happy.
To my knowledge I made zero changes to my setup since then (there may be changes I do not remember/aware of) and suddenly this parameter is ignored again!
This shows relevant sections of the log file:
Spectre (R) Circuit Simulator
Version 17.1.0.160.isr2 64bit -- 26 Jan 2018
Copyright (C) 1989-2017 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
[...]
Global user options:
vabstol = 1e-12
iabstol = 1e-12
temp = 27
gmin = 1e-12
gmin_check = all
rforce = 1
maxnotes = 5
maxwarns = 5
digits = 5
cols = 80
pivrel = 0.001
sensfile = ../psf/sens.output
checklimitdest = psf
noiseoff_type = 1
save = allpub
subcktprobelvl = 2
reltol = 1e-08
tnom = 25
scalem = 1
scale = 1
[...]
Now going into Results -> Print -> Noise Summary I get this:
This is clearly NOT noisetype_off=[flicker]!
According to the linked post I fixed the problem by moving from MMSIM15.1 ISR10 to SPECTRE16.
Now above you can see I use SPECTRE17 here but I went and used SPECTRE16 and also but it still does not work any more.
What else could be wrong here?
I am using the 6.1.7 version of cadence and I noticed that the switch instance in analoglib has the following cdf parameters. 
I was wondering if anyone could tell me why there are two fields for open switch resistance and closed switch resistance here. I looked at the reference manual for analogLib components in 6.1.7 and it only mentioned one field for open switch resistance and closed switch resistance.
Thanks
Hello,
I am trying to make use of the Monte Carlo option: dist=unif
with IC6.1.7 and SPECTRE 17, but I can not find any place to choose this option.
Is there a way to activate it?
Kind Regards,
Michael
In ADE L I could check the mosfet operation region with the "Device Checking" Tool. I recently switched to ADE Explorer and wanted to do there the same. However I cannot get to set up the wanted check in the "Checks/Assert" Form. I added ther the following data:
- Subs: My devices (eg. nmos4 pmos4)
- Param: region
- Values: tried 3, sat
- Analyses: dcOP
However it keeps saying that there are no violations but with the Device Checking Tool there are violations reported. How do I need to set up the Checks/Assert Form to achieve the same?
Kind regards
Lukas
Hi All,
I have a custom design in which (due to some reason I can't remember) I have the vdd and gnd as vdd! and gnd! (please note the exclamation!) at all levels of heirarchy. Now at the top-most level, I am connecting this vdd! a net/pin called VDDpwrDDSLL and of course, I have errors.
So, to resolve this I used the netSet property. netset vdd! = VDDpwrDDSLL but nothing changes and continues to give errors. This is affecting my cdl extraction as I am getting a failed netlist.
Apart from this I tried a couple of other things like using inherited connections, but somehow it gets messy.
Any ideas on this?
Thanks,
Kashif
Hello people,
today I have this problem, which should be easy to describe. I have a maestro view and I use it to run a simulation. This simulation includes a file which enables a huge list of asserts related to Safe Operating Area Checks.
My question is: is there an expression that I can use to see if an assert has been violated? If there is at least I violation, I will check the log but I don't want to open and check it if all asserts are satisfied.
I use ICADV 12.3
Thank you and best regards,
Patrik
Hello,
I have the GDS file of the layout. Is their any way to get the LEF file of the design through command line?
I want to write a VerilogA model which monitors input current and prints a message if it is above certain level. I also want output to be same as input current.
I wrote a model and it works but throws out below error when I add a line for output current to be equal to input. Any suggestions what I'm doing wrong here?
[code]`include "constants.vams"
`include "disciplines.vams"
module CurrentMonitor_VlogA(Iin,Iout);
input Iin;
output Iout;
electrical Iin,Iout;
real Ivalue;
parameter real IT2Limit=1m;
analog begin
Ivalue=I(Iin);
I(Iout)<+I(Iin);
if (Ivalue>=IT2Limit)
$strobe("WARNING:Value of current at node Iin has exceeded %g at %m, Iin=%g at simulation time t=%e",IT2Limit,Ivalue,$abstime);
else
$strobe("Current at node Iin=%g, simulation time=%e",Ivalue,$abstime);
end
endmodule[/code]
Here is the error message:
ERROR (SPECTRE-16384): Signal V(Iout) = -732.434 GV exceeds the blowup limit for the quantity `V' which is (1 GV). It is likely that the circuit is unstable. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
Hi,
I am using lsps_otc in my design. I had added guard ring (pring) and connected it to ground.
But when I run LVS it complains "missing instances" to all the lsps_otc.
May I know how to connect lsps_otc to ground?
Hello,
I have the GDS file of the layout. Is their any way to get the LEF file of the design through command line or script?
I can use uiLoadTrigger in CIW but si.log will complain it is undefined when do auCdl.
After debugging, this error should come from libInit.il under a PDK library.
Any ideas?
Thanks.
Fred
I have been able to set errpreset two ways:
1) command line +errpreset=conservative
2) spectre tran statement: tran tran stop=20n errpreset=conservative
Can this be specified in spice format .options ?
Hi,
I have a coworker I've been trying to help to get verilogAMS to run and to be able to run a simulation. At first verilogAMS wouldn't compile because it couldn't find the 64-bit version of ncvlog. After looking at the paths in the wrapper, i added the path to the 64-bit version in IC (I know there is also one under MMSIM). Anyways, this time it could find it, but it would not recognize "constants.vams" or other files unless I type the full path to it. After using the full path, the verilogams view compiled producing a symbol.
Now the problem is that my coworker is setting up a schematic with both veriloga and verilogams instances and then trying to run a simulation. We kept getting errors and when I read a little more, I found out that we need to use the AMS simulation tool, not spectre. We created a config view for the schematic and in ADE L, we set "ams" as the simulation tool. After that we get the following warning and error message in the CIW:
*WARNING* The Virtuoso Analog Design Environment (ADE) creates a user interface (UI) to match the features of the particular
version of IUS you are using. The software could not find the 'feature file' in the IUS hierarchy that lists the features
available in this version of IUS. You might be using a wrapper script around the simulator such that 'which ncsim' returns
your wrapper script and not the simulator in the IUS hierarchy. For now, ADE will create a UI to match the latest version
of the simulator. If you are using an older version and do not want to see the UI for features that are not available in
that version, you can set the following variable according to the simulator version you are using:
setenv AMS_FEATURE_FILE /home/pathForIUS/tools/affirma_ams/etc/files/amssim.dat
*Error* strcat: argument #1 should be either a string or a symbol (type template = "S") - nil
I tried to look for this "amssim.dat" file in our install directory for cadence tools so that I can add it to the wrapper, but II'm not sure where it is exactly. This is all new to me and I wish I could help my coworker more, so any help on how to setup and run a verilogAMS simulation would be helpful.
Thanks,
Miguel
After launch icfb, I got the following error:
X Error of failed request: BadName (named color or font does not exist)
Major opcode of failed request: 45 (X_OpenFont)
Serial number of failed request: 15
Current serial number in output stream: 30
could someone help?
thank in advance.
JM.
Hi All,
For the characterization of a standard cell library, I am using LIBERATE_15.14.070 version. The cell spice model was generated using IC6.1.5, and I am using Spectre as the external simulator for the characterization. I have a question specifically on the leakage_power nodes of the .lib file generated by Liberate. For an example, for a simple inverter, I ended up having leakage_power values as follows (in the link):
However the resulting leakage values do not follow the circuit simulation values in IC6-Spectre.
> Can anybody explain why the leakage value related to VSS pin is always 0 ?
> How does the Liberate calculate these values ? Is there a way to evaluate the accuracy of Liberate-Spectre simulation ?
Thanks in advance
Anuradha