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[URI] RelXpert support for HISIM_HV model cards.

April 11, 2018, 5:43 am
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Hello All,

I am implementating an aging model using the URI for a transistor techonology using a HISIM_HV model card.

The implementation works fine when I run the simulation using the Spectre Native option,  but when I try to do it using RelXpert, the tool produces  an error stating  that model level  is not supported.
It seems that the mistake comes when RelXpert parses the Netlist, even before the simulation begins

It is there any information regarding what Model Cards types are supported by RelXpert, or if the Model cards should be define in a specific manner, so RelXpert can use it.

Like I said before, the implementation works perfectly with Spectre Native reliability Block.

Thanks in advance for your help

Best Regards,

Fabio

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Image Rejection of IQ mixer

April 11, 2018, 6:08 pm
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What is the easiest way to simulate image rejection of an I/Q downconversion mixer - if possible with pss/pac?

Suppose the mixer is a black box with a PORT at the LO input (which generates 0 and 90 degree versions), a PORT at the RF input and two baseband outputs.

I can now use pss with the LO as beat frequency and set pac=1 for the RF input port.

With PAC I am sweeping from LO to LO+someOffset .... which makes a tone at the upper sideband. After downconversion, I should get signal energy in both I and Q channels.

In MATLAB (or a measurement) I would look at DFT(bb_i + j*bb_q) and read off the difference between the upper and lower sideband peaks. But in Spectre I am confused: I can use dB20(leafValue(mag(v("/vodi" ?result "pac")) "harmonic" -1)) and dB20(leafValue(mag(v("/vodq" ?result "pac")) "harmonic" -1)) to get the pac outputs but they are somewhat already in frequency domain. How do I combine them properly to read off the image rejection?

Or is there an easier way altogether?

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Error detected in psf library while writing to file `tran.tran'.

April 12, 2018, 2:42 am
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Hi,

I am using virtuoso to simulate my 30k gates design and in the process i am saving all the signals along with power signals.

After 2.5ms (2.27 %) of the simulation, i am getting a fatal error "  FATAL (SPECTRE-7035): write error on PSF file: Error detected in psf library while writing to file `tran.tran'." and the simulation gets terminated.

The simulation folder has >200GB memory available and the size of file tran.tran is 1.5GB.

Please suggest how to correct this error.

Thanks in advance.

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Changing x-value of a signal and/or handle signals with multiple outputs

April 13, 2018, 2:49 am
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Hello,

My question from https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38589/image-rejection-of-iq-mixer is still up :( So far I found the following hack: PSS+PAC, relative harmonic=1 and frequency sweep -100M ... 100M (for example). Then:

leafValue(v("/vodi" ?result "pac") "harmonic" -1) + (sqrt(-1) * leafValue(v("/vodq" ?result "pac") "harmonic" -1))

Similarly as combining the I/Q data in time domain I add them in frequency domain (pac data) as complex value. The problem is that this maps both the positive and negative frequencies to the same (positive) frequency values.

Question 1: When I plot this (or export to CSV/Table) one x value (e.g. 10 MHz) has 2 y values (one for positive and one for the negative frequency). How do I obtain the individual values? If I use value it just gives me the mean!

Question 2: Is there any way to modify the x-value of the pac data to include negative frequencies?

Thanks!

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How can you move/stretch schematic wires WITHOUT Virtuoso rerouting everything and making a mess?

April 13, 2018, 2:35 pm
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I did try searching for this answer, but got lost in the zillions of search results so I thought I'd try here...

I have a schematic that I've carefully and neatly laid out. If I edit it to do things like move instances or select regions of wires to stretch (all with wire rubber-banding in play) then Virtuoso steps in after I unclick my mouse and pretty much destroys my schematic layout with it's subsequent auto-routing. I realize some of this is to prevent errors like different wires landing on top of each other etc., however I've spent way, way more time cleaning up after some truly visually disgusting autoroutes that I'd rather always live with the danger of any errors I might create during my moving and stretching. Is there a way to configure Virtuoso to just take all the vertices and instances contained in my selection rectangle and yield straight line point to point wiring after I've done my edit? Bonus points if there's an optional way to constrain the movement of the selected set to be only in the X or Y direction.

Thanks.

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File Type Clarity - Using Built-in Capture Symbol Models to Create Non-Associated Custom Parts and Software Version Capabilities

April 14, 2018, 11:23 am
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What I'm trying to do...

      I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I change the modal name and parameters for one it only applies to that model), custom parts that have functionality and can be used in the same schematic. I've been trying for two days now and have read many articles, but still I don't clearly understand what's going on with all the different file types and  there functionality in the different programs (ie: lite/student versions of Pspice, Capture, Pspice-Model editor).

What I've tried to do so far...

     In Capture I add a part to the screen. Then, I select, right click the part and "Edit Pspice Model".. Then, in Model Editor I try to change the Model Name and a one off "part" the that will be the same king of device in my Schematics but with different parameters and a different model name. I've also tried to open Model Editor on it's own and make a library and add parts but it doesn't recognize the .OLB Breakout files.

What I don't Know...

      I don't know what the difference is between the file types (.LIB .OLB .MOD .OBJ) and I don't understand the association in models and libraries and (you name it). I understand that there maybe can also be different models based on locality, meaning simulation profile specific vs global library vs Schematic and such.

RESTATED. I just want individual N-Channel MOSFETs on the same schematic in Capture, Whose properties can be different (ie LAMBDA, VTO, W, L, ETC.) AND Whose names can be different.

Thank you in advance, to anyone that can help.

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IC617 import GDS file from TSMC.

April 14, 2018, 10:47 pm
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Hi, 

Can I ask a favor?

I am trying to import an io pad lib from TSMC into Cadence IC 617. This is how I tried to do it.

I firstly create a library , name it io_pad and attach it to my TSMC PDK library (tsmcN65).

Then in the CIW, file----import----stream

then choose Stream file: home/..../xxxxxx.gds

Library: io_pad 

then click translate. 

There are 0 error and 3 warnings. 

WARNING (XSTRM-75): Target library 'digital_cell' is attached to the technology library 'tsmcN65'. Therefore, the technology file is opened in read-only mode. All the undefined layer-purpose pairs will be dropped.
WARNING (XSTRM-107): Existing cells in the target library will be overwritten if the cell names in the Stream file and the target library are the same. To prevent this, set the '-writeMode' option to 'noOverwrite'.
WARNING (XSTRM-363): The technology library has been modified during XStream In translation. Cannot save the changes in the technology file because it is open in read-only mode.
Though I can see the io pad layout in the library, can anyone tell me what caused these warnings? Does these warnings matter?
Thanks
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Cadence simulation setup－core usage-

April 14, 2018, 10:59 pm
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Hi team

I have posted this question on other EE forums and received conflicted answers. But I think no where can give me a better answer then here. So here we go

Now I am using CADENCE IC 617 and MMSIM151 on a Linux machine with 10 cores CPU (20 threads). The simulation setup is like this:

ADE L --> Setup --> High-Performance Simulation Options. Then I click APS. choose Error Preset: DO not override; Use ++aps; Multi_Threading Manual #Threads: 19  (1-19)

But when I try to simulate, the total CPU usage is about 16% and a lot of cores are idle. The total simulation time-steps are 2210000 steps (transient time is 2210ns and simulation step is 0.001ns. ) this cost me more than 2 hours per simulation.

this is the info

[xxxxx@xxxxxx ~]$ top

top - 00:55:30 up 4 days,  2:38,  6 users,  load average: 2.00, 1.61, 1.57
Tasks: 422 total,   2 running, 419 sleeping,   0 stopped,   1 zombie
%Cpu(s): 10.1 us,  0.7 sy,  0.0 ni, 89.2 id,  0.0 wa,  0.0 hi,  0.0 si,  0.0 st
KiB Mem : 65727816 total,   538404 free,  3730288 used, 61459124 buff/cache
KiB Swap: 32964604 total, 31957960 free,  1006644 used. 61534544 avail Mem 

  PID      USER           PR   NI    VIRT            RES           SHR     S      %CPU    %MEM     TIME+       COMMAND    
 7718    xxxxxxxxxxxx 20    0      1744388    469288    4152    R     206.6     0.7            1460:39     spectre 

It seems the CPU is very underused. 

My questions are:

1. Does anyone know how I can setup the software to use all or most of the CPU power to speed up the simulation?

2. What dictate the time step of the simulation? 

Thank you very much
Allen

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Innovus CTS for a range of clock

April 15, 2018, 4:32 am
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Lets assume, I have a clock source whose frequency can very within a range (like within 6MHz to 9MHz range).I have a verilog circuit module where I would like to use this clock.

How can I configure Innovus to perform clock tree synthesis and post route synthesis so that this total circuit will not be susceptible to any  clock related violation (setup time, hold time etc.) within a particular frequency range? What kind of possible setup should I use ? 

thank you for  your time. 

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QRC Lvs Extracted View

April 15, 2018, 1:20 pm
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I am using QRC with LVS Extracted View output in order to generate the circuit netlist from the layout.

The netlist (created with ADE-L) is the reported below. However I would like to add a custom extra line in a given subckt section (i.e I0 (net1 net2) myblock) to include an additional parasitic model for my MEMS simulation.

Is there a method for adding such a line in a spectre netlist (i.e. nlPrintComment netlister ....)?

Thanks,

Pietro

// Library name: test
// Cell name: diode_Test_Top
// View name: av_extracted
// Inherited view list: spectre cmos_sch schematic veriloga ahdl
subckt diode_Test_Top D G S Sub
avD218_3 (NW2 I1\|net11) iprobe
avD218_2 (NW1 I1\|net11) iprobe
avD218_1 (SUBSUB Sub) iprobe

TO ADD: I0 (net1 net2) myblock


\#7cI1\|avD201_5 (Sub I1\|net11) nwdiode area=2.35472e-10 \
perimeter=0.00012938 dbv=0.0 m=1
\#7cI1\|avD201_4 (Sub I1\|net11) nwdiode area=6.4e-11 perimeter=3.2e-05 \
dbv=0.0 m=1 

....

....

ends diode_Test_Top
// End of subcircuit definition.

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PAC + PSS for a single-inductor multiple-output (SIMO) converter with verilogA

April 16, 2018, 6:59 pm
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I would like to run PAC + PSS for a single-inductor multiple-output (SIMO) converter to plot small signal transfer function from duty cycle to each ouput of the converter.  However, some blocks of the schematic are implemented in verilogA. So is it possible to find the small transfer function?

Thanks for help. 

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How to do "multiplication" in freq. domain with provided noise data file?

April 17, 2018, 5:08 am
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Hi all,

Recently I've been doing some noise evaluation issue, the simplified testing environment is as below:

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The thing I want to do is to multiply the noise profile defined in both "AVDD" and "TFsquared_AVDD2VCOVDD" sources.

This case is not as simple as that of a VCVS and a noise source since VCVS cannot read the extracted noise data file...

The noise sources are defined as follows:

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where "AVDD" noise was given in self-defined noise/freq pairs and "TFsquared_AVDD2VCOVDD" read the .txt noise file.

I tried to do multiplication by the ideal block "multiplier" defined in ahdlLib.

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Finally, I ran .noise simulation and plot output noise and instance noise individually.

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The first two rows are input noise sources and the final row is the resulting output noise.

It seems that the output noise is not like what I have expected, namely, the multiplication of row1 and row2.

Instead it is the summation of input sources...

I wonder if there is any way to do noise multiplication in Cadence Virtuoso environment?

I would be very grateful for all of your kind help:)

Thanks in advance.

Simulation environment

virtuoso 6.1.7-64b

spectre 16.1.0.440.isr8 32b

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Performance of BSIM-CMG 110.0.0 FinFET SPICE model in spectre simulator

April 17, 2018, 9:08 am
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Hello,

recently I got interested in the BSIM-CMG FinFET SPICE model.

Looking at the Verilog-A reference code I wonder what performance

can be achieved on current multi-core/multi-threading Xeons with

optimized C code.

I would be interested to learn what the evaluation time is for one

single iteration of latest BSIM-CMG in spectre.

I estimate ballpark in the tens of micro seconds but would be curious

to know from spectre R&D experts what the state of the art is here.

Thank You !

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flattening a cell in a library

April 17, 2018, 10:53 pm
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Hello!

I want to flatten a certain cell, say cell_A, inside all of the cells in a library that contain this cell_A.

How do I do it using a skill code?

TIA

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how to enforce identical MC mismatch variation on sub circuit used for calibration as those applied on the main test bench

April 18, 2018, 6:28 am
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good afternoon,

For a  high dynamic range CT SD ADC we need a few  calibrations prior to running MC process & mismatch verification. We were wondering about possibility to run these (analog) calibrations inside test suite using another test bench containing only the relevant sub circuits taken from  the main test bench, to save on compute resources as a single transient verification on ADC full schematic takes really a long time.  We then, for each MC iteration, need to enforce the same mismatch variations on the sub circuits used in the calibration testbench as will be applied on same sub circuits in main test bench.  Can this be accomplished with Maestro ?

kind regards

Hans

 

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Liberate for .lib generation of D flip flop

April 19, 2018, 5:02 am
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Hi,

I'm trying to characterize a D flip flop using Liberate_AMS. Here for the stimulus I'm creating a delay table (rather than using a test bench and using the define_deck command)....

I'm getting the delay values but not getting the setup and hold time to be characterized. I have verified the generated waveforms from the deck and its getting generated in a way so that the setup/hold time can get characterized. 

I have attached the snapshot of the delay table and also a snapshot of a portion of the log...

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Filter Layout pins from LVS

April 20, 2018, 2:12 am
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Hi,

The LVS extract some devices with 3 pins, while in the corresponding schematic device has 2 pins.

I need to extract the third pin in the layout in order to include a customized model.

Is it possible to filter the additional pin extracted by the LVS in order to have LVS clean?

Thanks,

 

Pietro

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Will different save options cause different Spectre simulation time?

April 20, 2018, 3:35 am
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Hi,

I’m using Spectre in ADE L to run simulation. When setting ‘selected’ in ‘Select signals to output(save)’, it elapsed about 135 seconds. Setting ‘allpub’, it elapsed about 172 seconds. Of course, the larger the circuit is, the more time difference between them. 

Does it make sense? In my opinion, no matter which setting I choose, the simulation should cover the whole circuit, or just result from disk I/O?

Thanks!

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Device parameters not netlisting in LVS

April 20, 2018, 11:05 am
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I am trying to netlist device parameters in LVS. I am using the standard measureParameter and nameParameter command. But the parameters are not getting netlisted. This is usually a simple operation and I've never had an issue with it. What could I be doing wrong that the parameter netlisting is failing? Should I look at something in the CDF setup? What other reasons might cause parameters fail to netlist?

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Suggestions for practical ADE Assembler test setup for corner-specific cellviews?

April 20, 2018, 12:55 pm
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Hi,

Our design teams use corner-based extraction cell libraries. These extractions are saved as various views in each cell. We are interested in convenient ways to specify distinct views per corner within an ADE Assembler test.We are not interested in breaking up to multiple tests as updates need to be synced across them.

We are aware that via config views, the CONFIG/<lib>/<cell> parameters can be set on a per-corner basis. This implies one parameter per master lib-cell, which means 10's-100's parameters. This could become untenable to keep them in sync throughout design updates.

Are there ways to simplify the Config view approach?  For example, accepting wildcard in the CONFIG parameter names, CONFIG/mylib/abc_*

We've considered using include <file> to include netlists, and change <file> per corner, but we found that include does not accept a variable filename.

Other approaches?

Our Virtuoso version is ICADV12.3-64b.500.9.

Thanks,

Henry

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