Hi,

I have a .scs model file for a digital block. The digital block has some multi-bit (bus) outputs. At the end of the .scs file, there are a bunch of statements to drive the outputs of the blocks:

v1 (demux\<0\> gnd) vsource type=dc dc=0

and this is repeated for each bit of the multi-bit signal.

This model file is added: ADE -> setup -> simulation files --> (added in the definition files category), and the testbench runs successfully.

Instead of driving each bit along, I would like to drive the whole bus (ideally with an analog value that gets translated during simulation). I have a VerilogA analog to digital component (tested and works) that I would like to use to drive that bus, the syntax that I used is:

AD1 (demux\<3\:0\>) adc_4b one=vdd zero=0 num=demux_val

At first the simulation failed complaining that adc_4b is not defined (although the library containing it is added to the library path in the library manager). I added the veriloga (.va) file that defines the component, once to setup--> simulation files --> definition files, and once to setup--> model files, and in both times the simulation fails because of a whole bunch of errors that seem to be VerilogA parsing errors, for example:

ERROR : (SFE - 874) "path" : unexpected quote character "`". Cannot run the simulation because of syntax error.

and so on.

veriloga is added to the switch view and stop view fields in setup --> environment

I am using IC6.1.7-64b.500.16

Thank you in advance

I am getting this error when tried to simulate ideal op-amp from library named 'functional'. Can someone help me to fix it.

Thanks,

Jaisal

how to run skill skill script from csh environment? I find the skill command from $install/tools/dfII/bin/skill, but skill command (for example schPlot) can not be executed in the skill shell.

Is there any way to add a new empty strip on ViVa? I would like to add a new one not split strip. Thanks.

I've looked over a couple previously posted solutions, e.g.:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/34307/default-colors-in-waveform-viewer

However I can't seem to make this work. I've tried opening the Display Resource Editor and tweaking y0-y9 without success. I continue to see waveforms as shown in the picture. Any ideas?

I have an on-going battle with Virtuoso trying to make things work and/or not look disgusting with everything on a white background (so I can always have WYSIWYG when I print stuff). I made my own display.drf file that contains (so far) only the things I need to make schematics look good on a white background. My most recent hurdle was figuring out what defined the color of selected items like wires or labels etc. Before I fixed it, that color was white (which annoyingly makes the selected items invisible on a white background). For the technology I'm using, the solution proved to be the following line in my display.drf file:

; color of selected items (lpp = align/drawing).
( display defaultPacket blank dashed red red outline )

However, I've since found as I bring more tools into the fold that I need to prevent my display.drf file from loading first because (for reasons unknown to me) it appears to block other display.drf files from other libraries loading. To get around that I added the following to my .cdsinit:

; Force Cadence to load the tsmc18 library and read it's display.drf file first
ddGetObj("tsmc18")~>techLibName
; Now superimpose my display.drf file on top of it
; The nil means it won't ask you to save it when you quit Virtuoso
drLoadDrf("./display.drf" nil)

After I do the above, everything in my schematics continues to look as per my display.drf *except* for the color of the selected items as outlined above - they're coming out as white again :-(.

I'm guessing maybe another rogue display.drf file is being loaded after mine, but darned if I know to determine or fix that. Any ideas?

Note that I realize I could just let everything load up, go into the Display Resource Editor and then merge my display.drf file into it and save the result (assuming "merge" means anything set in my file overrides existing stuff). However, that would become a maintenance nightmare after a while as I move from project to project.

Hi,

After an EM/IR run completes, the menu item: results > EM/IR Data > Report can generate non-selfheating-aware EM/IR text reports.

To get selfheating-aware EM/IR text reports, we open the viewer from EM/IR Data > Layout analysis...  let it load, and then type commands such as

print_em_report -net all_nets -type avg_sh -filename ./avg_sh.txt

at the Voltus-FI console.

Are there other ways create the selfheating-aware EM/IR text reports after a run? (Or a way to pass commands to an active VFI session from CIW, so a SKILL function can be used)

Here are things we have tried:

- An additional license is needed if we start a batch mode process. We have limited number of licenses.

- In Voltus-FI XL user guide, Table 4-1  Supported EMIR Control File Options listed that print_em_report=[...] can be used with emirutil in a control file. We tried adding

emirutil print_em_report=[net=all_nets type=avg_sh filename=avg_sh.txt]

to the prerun emir.conf, and to the viewer .conf file, but text reports were not created in both cases.

Thanks,

Henry

Hi,

I need help on several questions:

1, What's the difference between 'all' and 'allpub' in the save options form of ADE L? In the Cadence Help, I see that the difference is 'Voltage from an internal node in the device model or a Verlog-A module.', so what does this exactly mean? How to check the result of this entry?

2, No matter which I choose, 'all' or 'allpub', the simulation is always running over the whole circuit, and the result would be the same, am I right?

Thanks!

I am having a problem with running time in ADE L. I wrote a zero detector circuit in verilog A and added this to my schematic. However, I don't know why this caused the simulation is very very slow. It ran OK before adding this.

The circuit is somewhat complex and I am afraid of Cadence Online Support because it is usually slow to get response and not solve the problem. 

I would like to attach the output log with some warning about delay buffer and the zero dectector circuit in verilog A. Hope someone can tell me what is wrong here.

zero detector circuit in verilog A:

// VerilogA for SIMO, zeroDet, veriloga

`include "constants.vams"
`include "disciplines.vams"

module zeroDet(vin1,vin2,vout);
input vin1,vin2;
output vout;

//parameter delay=1n, trf=1n;

electrical vin1,vin2,vout;
real y1;

analog begin

if(V(vin1,vin2) > 0) begin
y1 = 1 ;
end

else begin
y1 = 0;
end

V(vout) <+ y1;end
//transition(y1,delay,trf)

endmodule

Output log:

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 12.1.1.048 32bit -- 4 Jun 2013
Copyright (C) 1989-2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: Huan Host: cnsl HostID: F88F4396 PID: 8973
Memory available: 15.8044 GB physical: 25.2701 GB
CPU Type: Intel(R) Xeon(R) CPU X5550 @ 2.67GHz
Processor PhysicalID CoreID Frequency
0 1 0 2660.1
1 1 1 2660.1
2 1 2 2660.1
3 1 3 2660.1
4 0 0 2660.1
5 0 1 2660.1
6 0 2 2660.1
7 0 3 2660.1

Simulating `input.scs' on cnsl at 2:14:00 PM, Thur Apr 26, 2018 (process id: 8973).
Current working directory: /home3/Huan/simulation/SIMO/spectre/schematic/netlist
Command line:
/tool/MMSIM12/tools/spectre/bin/32bit/spectre input.scs +escchars \
+log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre0_18098_3 -format psfxl -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 8973

Loading /tool/MMSIM12/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /tool/MMSIM12/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /tool/MMSIM12/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /tool/MMSIM12/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /tool/MMSIM12/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file: /home3/Huan/simulation/SIMO/spectre/schematic/netlist/input.scs
Reading file: /home3/Huan/Process/MS018/Project/SIMO/sah_ideal/veriloga/veriloga.va
Reading link: /tool/MMSIM12/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file: /tool/MMSIM12/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading link: /tool/MMSIM12/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file: /tool/MMSIM12/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading file: /home3/Huan/Process/MS018/Project/SIMO/errComp/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/not_gate/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/and_gate/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/adder_4/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/comparator/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/or_gate/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/nand_gate/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/nor_gate/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/soft_voltage_clamp/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/integrator/veriloga/veriloga.va
Reading file: /home3/Huan/Process/MS018/Project/SIMO/zeroDet/veriloga/veriloga.va

Time for NDB Parsing: CPU = 150.976 ms, elapsed = 155.938 ms.
Time accumulated: CPU = 150.976 ms, elapsed = 155.938 ms.
Peak resident memory used = 25.3 Mbytes.

Existing shared object for module sah_ideal is up to date.
Installed compiled interface for sah_ideal.
Existing shared object for module errComp is up to date.
Installed compiled interface for errComp.
Existing shared object for module not_gate is up to date.
Installed compiled interface for not_gate.
Existing shared object for module and_gate is up to date.
Installed compiled interface for and_gate.
Existing shared object for module adder_4 is up to date.
Installed compiled interface for adder_4.
Existing shared object for module comparator is up to date.
Installed compiled interface for comparator.
Existing shared object for module or_gate is up to date.
Installed compiled interface for or_gate.
Existing shared object for module nand_gate is up to date.
Installed compiled interface for nand_gate.
Existing shared object for module nor_gate is up to date.
Installed compiled interface for nor_gate.
Existing shared object for module soft_voltage_clamp is up to date.
Installed compiled interface for soft_voltage_clamp.
Existing shared object for module integrator is up to date.
Installed compiled interface for integrator.
Existing shared object for module zeroDet is up to date.
Installed compiled interface for zeroDet.

Time for Elaboration: CPU = 51.992 ms, elapsed = 52.4008 ms.
Time accumulated: CPU = 203.968 ms, elapsed = 208.664 ms.
Peak resident memory used = 28.6 Mbytes.

Time for EDB Visiting: CPU = 2.999 ms, elapsed = 2.60115 ms.
Time accumulated: CPU = 206.967 ms, elapsed = 211.671 ms.
Peak resident memory used = 29.1 Mbytes.

Notice from spectre during topology check.
Only one connection to node `net076'.

Circuit inventory:
nodes 85
adder_4 1
and_gate 11
capacitor 10
comparator 2
delay 1
errComp 1
inductor 1
integrator 1
nand_gate 2
nor_gate 2
not_gate 16
or_gate 2
relay 17
resistor 13
sah_ideal 4
soft_voltage_clamp 1
vcvs 5
vsource 10
zeroDet 1

Notice from spectre during initial setup.
Multithreading Enabled: 4 threads on system with 8 available processors.

Time for parsing: CPU = 6 ms, elapsed = 118.267 ms.
Time accumulated: CPU = 212.967 ms, elapsed = 330.276 ms.
Peak resident memory used = 30 Mbytes.

Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre0_18098_3, ).

Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.

***********************************************
Transient Analysis `tran': time = (0 s -> 1 ms)
***********************************************
Trying `homotopy = gmin' for initial conditions.
Trying `homotopy = source' for initial conditions.
Trying `homotopy = dptran' for initial conditions..
DC simulation time: CPU = 75.989 ms, elapsed = 76.937 ms.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 1 ms
step = 1 us
maxstep = 20 us
ic = all
useprevic = no
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS

tran: time = 1.002 us (100 m%), step = 490.8 as (49.1 p%)

Warning from spectre at time = 1.00202 us during transient analysis `tran'.
WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.
Warning from spectre at time = 1.00202 us during transient analysis `tran'.
WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.
Warning from spectre at time = 1.00202 us during transient analysis `tran'.
WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.
Warning from spectre at time = 1.00202 us during transient analysis `tran'.
WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.
Warning from spectre at time = 1.00202 us during transient analysis `tran'.
WARNING (CMI-2080): Saved timepoints in delay buffer have exceeded `32768'. Simulation may take too many timesteps.
Further occurrences of this warning will be suppressed.

tran: time = 1.002 us (100 m%), step = 755.2 as (75.5 p%)
tran: time = 1.002 us (100 m%), step = 493.5 as (49.3 p%)
tran: time = 1.002 us (100 m%), step = 140.4 as (14 p%)
tran: time = 1.002 us (100 m%), step = 348 as (34.8 p%)
tran: time = 1.002 us (100 m%), step = 248.1 as (24.8 p%)
tran: time = 1.002 us (100 m%), step = 321.3 as (32.1 p%)
tran: time = 1.002 us (100 m%), step = 384.6 as (38.5 p%)
tran: time = 1.002 us (100 m%), step = 446 as (44.6 p%)
tran: time = 1.002 us (100 m%), step = 151.6 as (15.2 p%)
tran: time = 1.002 us (100 m%), step = 830.9 as (83.1 p%)
tran: time = 1.002 us (100 m%), step = 695.7 as (69.6 p%)
tran: time = 1.002 us (100 m%), step = 220.8 as (22.1 p%)
tran: time = 1.002 us (100 m%), step = 282.9 as (28.3 p%)
tran: time = 1.002 us (100 m%), step = 562.8 as (56.3 p%)
tran: time = 1.002 us (100 m%), step = 642 as (64.2 p%)
tran: time = 1.002 us (100 m%), step = 225.3 as (22.5 p%)
tran: time = 1.002 us (100 m%), step = 148.1 as (14.8 p%)
tran: time = 1.002 us (100 m%), step = 915 as (91.5 p%)
tran: time = 1.002 us (100 m%), step = 632.7 as (63.3 p%)
tran: time = 1.002 us (100 m%), step = 527.6 as (52.8 p%)
tran: time = 1.002 us (100 m%), step = 180.3 as (18 p%)
tran: time = 1.002 us (100 m%), step = 566.3 as (56.6 p%)
tran: time = 1.002 us (100 m%), step = 591 as (59.1 p%)
tran: time = 1.002 us (100 m%), step = 837.2 as (83.7 p%)
tran: time = 1.002 us (100 m%), step = 658.2 as (65.8 p%)
tran: time = 1.002 us (100 m%), step = 379 as (37.9 p%)
tran: time = 1.002 us (100 m%), step = 471.4 as (47.1 p%)
tran: time = 1.002 us (100 m%), step = 394.4 as (39.4 p%)
tran: time = 1.002 us (100 m%), step = 551.7 as (55.2 p%)
tran: time = 1.002 us (100 m%), step = 468 as (46.8 p%)
tran: time = 1.002 us (100 m%), step = 322.9 as (32.3 p%)
tran: time = 1.002 us (100 m%), step = 353.9 as (35.4 p%)
tran: time = 1.002 us (100 m%), step = 735.7 as (73.6 p%)
tran: time = 1.002 us (100 m%), step = 639.1 as (63.9 p%)
tran: time = 1.002 us (100 m%), step = 690.1 as (69 p%)
tran: time = 1.002 us (100 m%), step = 242.6 as (24.3 p%)
tran: time = 1.002 us (100 m%), step = 400.8 as (40.1 p%)
tran: time = 1.002 us (100 m%), step = 362.4 as (36.2 p%)
tran: time = 1.002 us (100 m%), step = 506.2 as (50.6 p%)
tran: time = 1.002 us (100 m%), step = 841.1 as (84.1 p%)
tran: time = 1.002 us (100 m%), step = 850.6 as (85.1 p%)
tran: time = 1.002 us (100 m%), step = 264.6 as (26.5 p%)
tran: time = 1.002 us (100 m%), step = 141.3 as (14.1 p%)
tran: time = 1.002 us (100 m%), step = 229 as (22.9 p%)
tran: time = 1.002 us (100 m%), step = 705.7 as (70.6 p%)
tran: time = 1.002 us (100 m%), step = 506.6 as (50.7 p%)
tran: time = 1.002 us (100 m%), step = 313.8 as (31.4 p%)
tran: time = 1.003 us (100 m%), step = 480.5 as (48 p%)
tran: time = 1.003 us (100 m%), step = 127.8 as (12.8 p%)
tran: time = 1.003 us (100 m%), step = 703.2 as (70.3 p%)
tran: time = 1.003 us (100 m%), step = 428.7 as (42.9 p%)
tran: time = 1.003 us (100 m%), step = 171.1 as (17.1 p%)
tran: time = 1.003 us (100 m%), step = 504.6 as (50.5 p%)
tran: time = 1.003 us (100 m%), step = 634.3 as (63.4 p%)
tran: time = 1.003 us (100 m%), step = 474.1 as (47.4 p%)
tran: time = 1.003 us (100 m%), step = 151.8 as (15.2 p%)
tran: time = 1.003 us (100 m%), step = 641.6 as (64.2 p%)
tran: time = 1.003 us (100 m%), step = 537.7 as (53.8 p%)
tran: time = 1.003 us (100 m%), step = 790.7 as (79.1 p%)
tran: time = 1.003 us (100 m%), step = 755.7 as (75.6 p%)
tran: time = 1.003 us (100 m%), step = 328.9 as (32.9 p%)
tran: time = 1.003 us (100 m%), step = 233.1 as (23.3 p%)
tran: time = 1.003 us (100 m%), step = 206.6 as (20.7 p%)
tran: time = 1.003 us (100 m%), step = 448.3 as (44.8 p%)
tran: time = 1.003 us (100 m%), step = 296.2 as (29.6 p%)
tran: time = 1.003 us (100 m%), step = 131.8 as (13.2 p%)
tran: time = 1.003 us (100 m%), step = 552.3 as (55.2 p%)
tran: time = 1.003 us (100 m%), step = 179.4 as (17.9 p%)
tran: time = 1.003 us (100 m%), step = 190.1 as (19 p%)
tran: time = 1.003 us (100 m%), step = 557.9 as (55.8 p%)
tran: time = 1.003 us (100 m%), step = 154.7 as (15.5 p%)
tran: time = 1.003 us (100 m%), step = 923.5 as (92.3 p%)
tran: time = 1.003 us (100 m%), step = 927.9 as (92.8 p%)
tran: time = 1.003 us (100 m%), step = 265.8 as (26.6 p%)
tran: time = 1.003 us (100 m%), step = 599 as (59.9 p%)
tran: time = 1.003 us (100 m%), step = 368.4 as (36.8 p%)
tran: time = 1.003 us (100 m%), step = 306.9 as (30.7 p%)
tran: time = 1.003 us (100 m%), step = 772.4 as (77.2 p%)
tran: time = 1.003 us (100 m%), step = 514 as (51.4 p%)
tran: time = 1.003 us (100 m%), step = 561.6 as (56.2 p%)
tran: time = 1.003 us (100 m%), step = 661.2 as (66.1 p%)
tran: time = 1.003 us (100 m%), step = 154.6 as (15.5 p%)
tran: time = 1.003 us (100 m%), step = 176.5 as (17.6 p%)
tran: time = 1.003 us (100 m%), step = 153.4 as (15.3 p%)
tran: time = 1.003 us (100 m%), step = 277.7 as (27.8 p%)
tran: time = 1.003 us (100 m%), step = 554.4 as (55.4 p%)
tran: time = 1.003 us (100 m%), step = 483.7 as (48.4 p%)
tran: time = 1.003 us (100 m%), step = 553.4 as (55.3 p%)
tran: time = 1.003 us (100 m%), step = 875.3 as (87.5 p%)
tran: time = 1.003 us (100 m%), step = 523.8 as (52.4 p%)
tran: time = 1.003 us (100 m%), step = 819.8 as (82 p%)
tran: time = 1.003 us (100 m%), step = 228.4 as (22.8 p%)
tran: time = 1.003 us (100 m%), step = 319.6 as (32 p%)
tran: time = 1.003 us (100 m%), step = 534 as (53.4 p%)
tran: time = 1.003 us (100 m%), step = 287 as (28.7 p%)
tran: time = 1.003 us (100 m%), step = 202.2 as (20.2 p%)
tran: time = 1.003 us (100 m%), step = 532.1 as (53.2 p%)
tran: time = 1.003 us (100 m%), step = 851.3 as (85.1 p%)
tran: time = 1.003 us (100 m%), step = 153.5 as (15.4 p%)
tran: time = 1.003 us (100 m%), step = 666.7 as (66.7 p%)
tran: time = 1.003 us (100 m%), step = 316.2 as (31.6 p%)
tran: time = 1.003 us (100 m%), step = 225.9 as (22.6 p%)
tran: time = 1.003 us (100 m%), step = 317.1 as (31.7 p%)
tran: time = 1.003 us (100 m%), step = 609.6 as (61 p%)
tran: time = 1.003 us (100 m%), step = 730.3 as (73 p%)
tran: time = 1.003 us (100 m%), step = 259.4 as (25.9 p%)
tran: time = 1.003 us (100 m%), step = 413.2 as (41.3 p%)
tran: time = 1.003 us (100 m%), step = 682.6 as (68.3 p%)
tran: time = 1.003 us (100 m%), step = 190.5 as (19.1 p%)
tran: time = 1.003 us (100 m%), step = 508.9 as (50.9 p%)
tran: time = 1.003 us (100 m%), step = 755.1 as (75.5 p%)
tran: time = 1.003 us (100 m%), step = 395.8 as (39.6 p%)
tran: time = 1.003 us (100 m%), step = 726 as (72.6 p%)
tran: time = 1.003 us (100 m%), step = 634.6 as (63.5 p%)
tran: time = 1.003 us (100 m%), step = 415.1 as (41.5 p%)
tran: time = 1.003 us (100 m%), step = 505.3 as (50.5 p%)
tran: time = 1.003 us (100 m%), step = 676.2 as (67.6 p%)
tran: time = 1.003 us (100 m%), step = 398.9 as (39.9 p%)
tran: time = 1.003 us (100 m%), step = 309.7 as (31 p%)
tran: time = 1.003 us (100 m%), step = 843 as (84.3 p%)
tran: time = 1.003 us (100 m%), step = 607.9 as (60.8 p%)
tran: time = 1.003 us (100 m%), step = 699 as (69.9 p%)
tran: time = 1.003 us (100 m%), step = 274.8 as (27.5 p%)
tran: time = 1.003 us (100 m%), step = 152.3 as (15.2 p%)
tran: time = 1.003 us (100 m%), step = 357.8 as (35.8 p%)
tran: time = 1.003 us (100 m%), step = 310.5 as (31.1 p%)
tran: time = 1.003 us (100 m%), step = 157.7 as (15.8 p%)
tran: time = 1.003 us (100 m%), step = 252.6 as (25.3 p%)
tran: time = 1.003 us (100 m%), step = 941.9 as (94.2 p%)
tran: time = 1.003 us (100 m%), step = 451.2 as (45.1 p%)
tran: time = 1.003 us (100 m%), step = 277.1 as (27.7 p%)
tran: time = 1.003 us (100 m%), step = 388.5 as (38.8 p%)
tran: time = 1.003 us (100 m%), step = 260.8 as (26.1 p%)
tran: time = 1.003 us (100 m%), step = 452.5 as (45.2 p%)
tran: time = 1.003 us (100 m%), step = 194.4 as (19.4 p%)
tran: time = 1.003 us (100 m%), step = 350.3 as (35 p%)

Hi all,

I'm trying to plot a DNL and INL od DAC across all the codes.
I run simple DC sweep simulation and I already have Calculator expressions for DNL and INL.
Now I would like to run MC simulation and calculate standard deviation of every for every DAC output step to see for which input code change the DNL is the worst.
I know it is possible with Matlab (never tried it) but is it also possible with OCEAN script?
Thanks
Adam

Hi All.

In IC 5.1.41 in ADE -> Simulation -> Options -> Analog

There were settings for compatibility spice2.

Where are these settings in IC6.1.7?

I really need them.

Hi everyone,

I've started a few months ago working on Cadence Virtuoso 6.1.7 and I've been able to import models using this guide (e.g. this model), unfortunately it doesn't work for some particular .lib files.

In particular I'm trying to import this model file for the THS4521, but, although it's a pspice model, it won't simulate through ADE.

A subset of the errors output by the simulator are as follows:

community.cadence.com/.../error.txt

Does anyone have any idea on how to import this model?

Thank you very much in advance,

Raffaele Aaron

Hello,

1. Assura may need to be installed separately. However, is Diva always installed alongside Virtuoso?

a) which executable file or shared libraries (.so), or paths should we check for Dvia's existence?

2.

This is an excerpt from "~ /1P6M_1.8V_3.3V_MM_RF/Assura/drc/drc.rul". Although it is listed under folder named Assura, almost all commands are Diva commands/syntax.

a) Is Assura a superset of Diva and supports all Diva commands?

b) Given that there is RCX tool (Dracula to Assura) exists which converts Dracula to Assura, and in view of the many same commands in Assura .rul files as to those in Diva .rul files, is there any official tool for converting Assura .rul to Diva .rul file?

3)

I am confused between Diva and Dracula. From GXL>Verify, Virtuoso seems to be prepared to launch Diva (from the divaDRC.rul filename). Is Diva the default choice for verification, instead of Dracula?

G

I would like to plot large signal transfer function from duty cycle to output voltage of a simple dc-dc converter such as buck converter. How can I do this? Thanks.

I get the message in the title when I try to simulate my circuit. The circuit contains a symbol of a custom device which I described in Verilog-A code. I know the Verilog-A code should work because I just copy/pasted it from a code which has worked in the past. How can I resolve this issue?

Below is the full error message.

I was working with ModGen two weeks ago and it was fine. Now, I wanted to go back and do some modifications but I cannot open the menu! I used the following path:

Windows -> Assistant -> Constraint manager

But now, I do not have such menu which seems quite weird. Here is the screenshot:

Does anyone know what is the problem and how can I solve it? Briefly, I want to see the window on the right side of the Cadence to be able to edit ModGens and create new ones. Cadence Version is IC6.1.6-64b.500.6. Thanks.

Hi everyone,

I use Opamp in adhLib to simulate the inverting voltage circuit.

with input Voltage is linear funtion in range -1 to 1 ( I use Vpwlf to make it)

My point is with input Voltage in [-1;0], the ouput of opamp is zero. And with voltage in [0;1], the ouput is inverted to [0; -1].

So I use Single Supply Voltage.

This is my circuit and results.

Can you tell me why I cannot get my point?

Thank you

I wanted to know if there was a method for varying the temperature with time. How might one go about doing this?

Thank you

Hi,

Although for top-level components, layout GXL works find and we can auto route connection, "auto route" does not appear to work between different level of hierarchies.

For example, in the attached screenshot, auto route does not connect top level FETS to the block in lower right.

Is this by design?

G

Îs there a way to blacklist/whitelist dedicated models from a PDK ?

I my case, we do have a PDK with different models for a MOSFET - standard models ("nch") and macro models (nch_mac").

The macro models ("nch_mac") are allowed to be used in schematic design, the other models shall be avoided/forbidden.

How can I forbid the usage of these models or create a warning when used ?