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xrun: *E,FILEMIS: Cannot find the provided file ./netlist.vams

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First, I am *very* new to Virtuoso, please be gentle!  Something isn't right with Xcelium simulations.

I am working through sanity testing the simulator.  I have a simple schematic cell view that I created with an analogLib.VDC, my own inverter, and a ahdlLib.resistor.  I also added supplies vdd and gnd.  I created a config cell view:   VDC is using the spectre view, res is using veriloga, my inverter is using behaviorial, and the test is contained in a schematic view.  I used the "AMS" template to for the cell view.   From there I launch either ADE Explorer or ADE L (the end results are the same).  I'll describe the ADE Explorer path. 

I selected the ams simulator, with a transient analysis, using the Spectre solver.  Using the "AMS Unified Netlister with xrun" option, the system fails to create a netlist (results follow), but using the  "Cellview-based" netlist option, the netlist generates and the simulation works exactly as expected.  Because I am new to the tools, I cannot tell if the problem is in the interface between chair and keyboard  or if its an installation issue or something else.

What I believe are relevant entries from netlist.log: 

Begin Netlisting Mar 17 11:09:37 2018
<snip>
INFO (VLOGNET-117): Re-netlisting the entire design.

INFO (VLOGNET-118): Using connection by name (explicit connections) for all
stopping and non-stopping cells

CELL NAME VIEW NAME NOTE
--------- --------- ----
res veriloga *Stopping View*
vdc spectre *Stopping View*
inverter behavioral *Stopping View*
basic schematic
---------- End of netlist configuration information ----------
Running netlist assembly..
End netlisting Mar 17 11:09:44 2018

From the job log:


Program: @(#)$CDS: virtuoso version 6.1.7-64b 11/21/2017 20:39 (sjfhw301) $
\o Hierarchy: /opt/cadence/IC617/tools.lnx86/dfII/
\o Sub version: sub-version IC6.1.7-64b.500.16 (64-bit addresses)
...
### Generating design information at:/home/cadence/cadence/simulation/tutorial/inverter_test/maestro/results/maestro/ExplorerRun.0/1/tutorial:inverter_test:1/netlist ###
\o ERROR (AMS-1245): AMS CBN netlisting has failed because of errors in the design.
\o Right-click the test name on the Outputs assistant pane
\o and check Output Log->Netlister Log for errors.
\o Correct your design and netlist again.
\o ...unsuccessful.
\e *Error* Error during netlisting of design for the point ID (0 1).
\e ("error" 0 t nil ("*Error* "))
\o *Error* Error ID = 5012
\o *Error* Error Msg = Failed to create netlist.

Finally, the simulation terminates with xrun.log:

xrun: *E,FILEMIS: Cannot find the provided file ./netlist.vams

However, Changing only the "Netlist and Run Options" to use the "Cellview-based" the simulation works exactly as expected.

Nothing appears to be segfaulting, and nothing else looks out of place.  


hidden some cell in pdk library

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there are too many cells in pdk library, but only partial cells will be used in the design, and I want to hidden the others that unused in the design.

how can I do it? I am try to use "View->filters" in library manger, but it will filter cells in all library.

Power IR/EM vs Voltus-Fi

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Hi All.

I understand correctly that there are two tools for IR/EM analysis?
Can anyone explain what difference between "Power IR/EM" vs "Voltus-Fi"?

Post layout simulation using Ocean Script

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Hello,

I want to run the post layout simulation using ocean script. But i am not able to find the keywords that i need to include in my ocean script to do post layout simulation.

I would be very thankful if you can help with this.

Request - Skill script for block level floor planning (Constant area stretch)

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I have browsed the forums for a number of years for ideas and references when creating some useful bind keys.

Recently I thought about a nice feature to have, would be to place down a rectangle or polygon as an area estimate in any layer and then be able to stretch it from a given side and maintain the area.

So basically you could reshape the figure, but always maintain a constant area.  Perhaps 4 bindkeys that stretch +/- in each direction by a given amount, (+/-10u) for example.

It would be great to have the area attached to the shape.  I think the hardest part would be the constant area stretch part.  I was hoping for some help on getting started with going down this route or if there is something that has already been done that is similar, that would be great also.

Thanks

Convergence problems using analogLib switch (DC simulation)

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Dear all,

I am doing a simple testbench for a comparator and would like to have several voltage sources, for different type of analysis, but only one common input on the comparator.

So I've defined the name of the comparator's input to be "stimuli" and the voltage sources to be called: sine, pulse and step.

Zoom of the previous figure

I know that the schematic above won't work for many reasons, but I just want to make clear what I would like to do. But even with one switch only, the DC simulation won't converge.

Many thanks.

Best regards,

Pedro

eyeDiagram() vs. Measurement --> Eye Diagram trigger period

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Hi,

in the result browser, the Measurement --> EyeDiagram lets me plot an eye diagram vs. a trigger periode generated from another signal - that's what I need.

The function "eyeDiagram()" only allows a constant trigger period - that is not what I want, because over corners the trigger period changes, and I want to get the eye diagram over corners.

How can I create an eyeDiagram() function with trigger period derived from another signal ?

Spectre simulation of verilogA file

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Dear All,

        My schematic consists of a dc voltage source and a simple resistor written in verilogA, just to understand how to use verilogA files with Virtuoso ADE. The netlist from Virtuoso ADEL -> Simulation -> Netlist -> Display is as follows:

// Generated for: spectre
// Generated on: Mar 23 01:58:58 2018
// Design library name: labs
// Design cell name: testing_verilogA
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: labs
// Cell name: testing_verilogA
// View name: schematic
V0 (net2 0) vsource dc=1.2 type=dc
I0 (net2 0) resistor_verilogA r=1
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
dc dc dev=V0 param=dc start=0 stop=1.2 write="spectre.dc" oppoint=rawfile \
    maxiters=150 maxsteps=10000 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save I0:in
saveOptions options save=allpub
ahdl_include "/home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va"

        After running the dc simulation, the error in my Virtuoso CDS.log window is:

ERROR (ADE-3036): Errors encountered during simulation. The simulator run log has not been generated.

Possible cause could be an invalid command line option for the version of the simulator

you are running. Choose Setup->Environment and verify that the command line options

specified in the userCmdLineOption field are supported for the simulator.

Alternatively, run the simulator standalone using the runSimulation file in the netlist

directory to know the exact cause of the error.

        So I went to my netlist directory from my terminal and used the ./runSimulation command. The resulting output is as follows:

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
        Security, Inc.

User: sv376   Host: en-ec-ph314-10.ece.cornell.edu   HostID: FD80C911   PID:
        31974
Memory  available: 6.5414 GB  physical: 16.5123 GB
Linux   : Red Hat Enterprise Linux Server release 7.4 (Maipo)
CPU Type: Intel(R) Core(TM) i7-6700 CPU @ 3.40GHz
        Socket: Processors [Frequency] (Hyperthreaded Processor)
        0:       0 [3576.1] (  4 ),  1 [3850.0] (  5 ),  2 [3856.1] (  6 )
                 3 [3949.8] (  7 )
        
System load averages (1min, 5min, 15min) : 1.2 %, 1.9 %, 2.9 %
Hyperthreading is enabled


Simulating `input.scs' on en-ec-ph314-10.ece.cornell.edu at 1:59:53 AM, Fri Mar
        23, 2018 (process id: 31974).
Current working directory:
        /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist

Warning from spectre.
    WARNING (CMI-2015): Unable to open log file `../psf/spectre.out'.
        Success.
Reading file:
        /home/sv376/Cadence/labs/testing_verilogA/spectre/schematic/netlist/input.scs
Reading link:  /opt/cadence/mmsim
Reading file:
        /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /usr/include/stdc-predef.h
Reading file:
        /home/sv376/Cadence/AHDL_stuff/resistor_verilogA/veriloga/veriloga.va
Reading file:
        /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:
        /opt/cadence/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Time for NDB Parsing: CPU = 46.849 ms, elapsed = 127.028 ms.
Time accumulated: CPU = 58.888 ms, elapsed = 127.031 ms.
Peak resident memory used = 31.4 Mbytes.


The CPU load for active processors is :
        Spectre  0 (30.8 %)      1 (7.7 %)       2 (7.7 %)       4 (7.7 %)
                 6 (8.3 %)       7 (9.1 %)      
        Other   

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1024): Unable to create directory input.ahdlSimDB/ (775)
    ERROR (VACOMP-1024): Unable to create directory
        input.ahdlSimDB//.resistor_verilogA.ahdlcmi/ (775)
    ERROR (VACOMP-1024): Unable to create directory
        input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/ (775)
    ERROR (VACOMP-2252): Cannot open file:
        input.ahdlSimDB//.resistor_verilogA.ahdlcmi/Linux/resistor_verilogA.lst
        - C-code will not be generated !!!

Reading link:  /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading link:  /opt/cadence/mmsim/tools.lnx86/spectre/etc/ahdl/constants.h
Time for Elaboration: CPU = 19.989 ms, elapsed = 25.1319 ms.
Time accumulated: CPU = 78.993 ms, elapsed = 152.279 ms.
Peak resident memory used = 38.1 Mbytes.


Aggregate audit (1:59:53 AM, Fri Mar 23, 2018):
Time used: CPU = 79.1 ms, elapsed = 152 ms, util. = 51.9%.
Time spent in licensing: elapsed = 14.6 ms, percentage of total = 9.56%.
Peak memory used = 38.2 Mbytes.
Simulation started at: 1:59:53 AM, Fri Mar 23, 2018, ended at: 1:59:53 AM, Fri
        Mar 23, 2018, with elapsed time (wall clock): 152 ms.
spectre completes with 4 errors, 1 warning, and 0 notices.

        At this point, I have tried web searches and the forum and to see how to resolve 'unable to create directory ....' errors that occur above. Why is spectre unable to create the above directories? How can I resolve this issue? I appreciate any help I can get. Thank you!

Regards,

Krishnaa


test please delete

ADE Explorer Real time tuning with schematic DC annotations

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When you run a DC analysis you can annotate the voltages and currents on the schematic.

Is there any way to use this with ADE Explorer's real time tuning?

ADE Explorer won't let the mode run without an output and if I supply one then the annotations disappear and the annotation options are greyed out.

Power MOSFET/IGBT in Cadence

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Hi,

We know that Virtuso is the standard for analog IC. That being said, power MOSFET is also important in analog design, but it doesn’t have simple geometry as PMOSs. They have VDMOS and other geometries and are not easily modeled in layout XL.

I also looked at TSMC PDK other PDKs and they don’t have power MOSFET primitives.

1. Does cadence offer any tool for power MOSFET and IGBT like designs? Do they have standard/parameterized cells as for digital logic?

2. There are TCAD tools lke Sentaurus for power MOSFET design. Are their design's resultant layout compatible with GDSII? Can Cadence import them?

Customer

Crude auto-layout SKILL to Virtuoso

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Hi,

In virtuoso, one can add Verilog type Cellview, and it can get compiled. For the least, this result in RTL netlist.

For millions of registers, one definitely needs Encounter for layout generation. However, some small functional chips might have just few hundreds of registers like for simple CPLD. In this case, there is not such strict timing constraint and the more liberty to take in placing the registers.

If one uses simple tools like Yosys (several MBs) to create RTL, then writing some simple computational geometry algorithm to do the layout (for small number), and convert the result to SKILL commands which do the placement, run the SKILL in Virtuoso CIW, we might get a less-than-optimal automatically generated layout. We can then carefully check Diva/Dracula/LVS rules, and get the result to pass verification.

If we try this approach, is there any particular pitfalls to be wary of?

customer

Full OSSHNL error list

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Hi,

Occasionally we get error message:

ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.

                simDcmFIlePath

 

But searching with “OSSHNL” prefix shows nothing in help. Is there a list of all OSSHNL errors, like for example Windows Error Codes?

 

 

G

NC-verilog Executable blank

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Hi,

When working with NC-Verilog, we get “executable” blank error.

In the forum there are also post1,post2 which suggest it is related to INCISIV installation. So is it imperative to install INCISIV to run NC-Verilog simulation? Is there any other fix? 

 

G

encounter invoke rc executable?

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Hi,

The rc command, found in socencounter/bin folder, as described in rc_user.pdf, provides many basic functionalities.

The SoC Encounter program, when we click Design>>Import RTL, does it actually invoke rc to do the work?

G


Playground Timing lab and constraint?

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Hi,

We would like to get familiar with some basic steps in encounter design. If we want to import some most simple Verilog in encounter, it asks for Timing lab and constraint. Is there any default Lib and constraint (loose constraint) to play with? Is there any tutorial folder coming with the installation containing them?

 

G

saveNetlist option changing view to functional from schematic- Innovus to Calibre

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Hello All,

I am performing an LVS run using Calibre. For this, I imported the stream/gds file and the the verilog file after my backend flow (Innovus).  The .v file was converted to a SPICE netlist  (not sure how..but if anyone could explain it a bit would be an additional help!!)

So now coming to the issue at hand,
the LVS was not an absolute match because of the presence of DECAPS which are there in the layout but not in the extracted schematic from the verilog.
So, to resolve this I added the option -includePhysicalCell {string/name of the decap cells} -includePhysicalInst in the saveNetlist option (in Innovus), extracted once again and performed a new LVS run. But now, the problem is that the top level is no longer schematic. It has changed to functional. 
Any ideas how to resolve this issue?
Thanks,
Cheers,
Kashif

Back Annotation of Segmented Resistors

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We have a situation where a single resistor device is placed in a schematic. Then in layout, the designer segmented the resistor into two series resistors. The device has a CDF parameter called "Segments" which has been set to 2.

LVS is clean and we can extract a DSPF via Cadence QRC.

When the DSPF is then ran in Specter sim, we do not get 100% back annotation because the Spice NL from the schematic does not contain the extra resistor and series Net present in the DSPF.

Has anyone ran into this issue? If so how did you resolve it without post processing the DSPF?

Shane.

CDF doneProc callback no longer runs.

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I have a symbol that sets some CDF parameters using a callback with the doneProc event.

I now get the following error "*WARNING* An error occurred while applying the CDF doneProc 'X' to (db:0x17f5a99a)"

(X is put in place of the name of the callback)

The error is quite vague so I'm not sure what to do

pnoise analysis modulated type for single edge

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Hello,

Is it possible to have pnoise analysis of modulated type while considering only rising edge. Meaning ignoring falling edge or dutycycle. Only rising to rising. It can be done in  pnoise "jitter" type , can it also be done in "modulated" type.

thanks for any input,

Kristopher

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