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Syntax for device checks associated to just one type of simulation

March 5, 2018, 11:46 pm
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Hello,

I am creating a number of device checks in ADE using a separate file (devcheck.scs let's say). I wondered if there was a way to specify that a check just be performed against one type of simulation. This type of operation is possible using the GUI Device Checks panel from what I can see but I would like to know the syntax for how to write such a limited check in a file.

Alternatively perhaps there is a way to output my checks from the GUI to a text file so I can create my check interactively and then create the inlcude file afterwards.

Any suggestions from anyone?

Many thanks,

Matthew Cordrey-Gale

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Cadence Custom Layout for beginners -RF IC design

March 6, 2018, 6:22 pm
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Cadence Custom Layout for beginners -RF IC design It's the first time that I am creating a layout for an LNA design at 35Ghz. What should I read or watch for understanding how to create the layout, metals, how to use the rules of the manual etc?
Thanks!
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leHiCreateVia

March 6, 2018, 8:38 pm
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Hi,

     I am facing an issue while placing via in layout. when I press 'o' in layout window it will execute 'leHiCreateVia' function and gives me an option to create via. If I create via this way by default all the layers are in 'drawing layer', whereas in pdk they are mentioned to be in 'logic layer'. If I create via by instantiating it by pressing key-i all the layers are in logic layer. Is there any way to change the layers to logic by default when i press key-o to create via.

Thanks,

Aswani Kumar.

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Verilog-A import variables from file

March 6, 2018, 11:17 pm
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I do have a lot (really a lot) of different variables in my Verilog-a model, like

real var_00=0001;

real var_01=0002;

...

real var_FF=0003;

As the huge number of variables make my code unreadable and confusing, I want to import these variables from an file.

How can I do that ?

What format is required for the file ?

I want to use these variables as simple local variables in my code.

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dynamic parameter in SpectreMDL

March 6, 2018, 11:58 pm
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Hi, 

    Basis: there is a need for me to change the temperature within the transient simulation.  I followed the post as linked below, and got it working in Spectre from ADE

   https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/10265/varying-the-temperature-in-a-transient-simulation 

    Problem: as the data extraction is huge, I have been using spectremdl to run the simulation, now with the "temp" as dynamic parameter, there is no change in expected results, the changes are obvious in ADE simulation though.  I have extracted the netlist from the test bench that worked well in ADE. 

   simple test case:  

   the tran control reads: 

             tran tran stop=1u param=temp param_vec=[0 27 315n 27 316n -20 416n -20 417n 100 517n 100 518n 40 618n 40] write="spectre.ic" writefinal="spectre.fc" annotate=status maxiters=5

   my spectremdl control file reads:

           t1 = temp @ 275n

           t2 = temp @ 375n 

           t3  = temp @ 475n 

but t1, t2, t3 all end up as same value. (T2=T3=T1=27) 

So, I am wondering whether the option is supported in spectremdl? or am i missing anything here? 

Thanks!

Aarthy

 

  

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FILL* on schematic unbound LVS error

March 7, 2018, 3:10 am
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I have imported my .cdl netlist file which contains all the standard cell connection information along with FILL and ENDCAP cells. Normally due to unbound error, I have to run LVS with "abortOnUnboundDevice" nil on. My LVS gives this error:

ERROR    Device 'ENDCAP(Generic)' on schematic is unbound to any Layout device.,

ERROR    Device 'FILL1(Generic)' on schematic is unbound to any Layout device.,

ERROR    Device 'FILL2(Generic)' on schematic is unbound to any Layout device.,

How could I solve this problem? Is there any problem with my filler standard cell library design ? I'm using ASSURA LVS check. 

I can avoid this error by deleting all the filler and endcap information from netlist as they do not have anything to do with schematic of the circuit. They have no physical connection with any block of the circuit. Is it ok ? I would really like a solution without any manual modification of the netlist design.

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How could I assign IO type during " Create Pins from Labels" option

March 7, 2018, 3:12 am
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When I import .gds from INNOVUS , there is no pins but labels. So I have to use "Create Pins from Labels" tool to place pins. But all the pins IO type are "inputoutput". How could I define IO types so that, I don't have to make it manually after using "Create Pins from Labels" . How can I do that? or I'm missing some command during PnR in INNOVUS  that I'm facing this problem?

Thank You for your time :)

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problem with lvs in calibre

March 7, 2018, 5:08 am
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hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors . i encountered some problems . it gives 16 error which 4 of them is saying "incorrect instances" and point to the 4 spiral inductors . 3 of them is saying incorrect ports and point to the vdd , gnd and input port . another 9 errors say incorrect net and i dont know they are about what ! can someone help me with this errors community.cadence.com/.../layout.rar i attached the file of  my layout and my schematiccommunity.cadence.com/.../schematic.rar

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saveNetlist option changing view to functional from schematic- Innovus to Calibre

March 7, 2018, 11:52 am
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Hello All,

I am performing an LVS run using Calibre. For this, I imported the stream/gds file and the the verilog file after my backend flow (Innovus).  The .v file was converted to a SPICE netlist  (not sure how..but if anyone could explain it a bit would be an additional help!!)

So now coming to the issue at hand,
the LVS was not an absolute match because of the presence of DECAPS which are there in the layout but not in the extracted schematic from the verilog.
So, to resolve this I added the option -includePhysicalCell {string/name of the decap cells} -includePhysicalInst in the saveNetlist option (in Innovus), extracted once again and performed a new LVS run. But now, the problem is that the top level is no longer schematic. It has changed to functional. 
Any ideas how to resolve this issue?
Thanks,
Cheers,
Kashif
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Back Annotation of Segmented Resistors

March 7, 2018, 12:26 pm
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We have a situation where a single resistor device is placed in a schematic. Then in layout, the designer segmented the resistor into two series resistors. The device has a CDF parameter called "Segments" which has been set to 2.

LVS is clean and we can extract a DSPF via Cadence QRC.

When the DSPF is then ran in Specter sim, we do not get 100% back annotation because the Spice NL from the schematic does not contain the extra resistor and series Net present in the DSPF.

Has anyone ran into this issue? If so how did you resolve it without post processing the DSPF?

Shane.

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Retain settings in Visualisation & Analysis Tool

March 8, 2018, 10:52 pm
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Hi,

In the Visualisation & Analysis Tool, I split up some of the waveforms to different stripes or I move some of the waveforms to an additional subwindow. However when I start a new simulation, all my changes are resetted. Eg. the curves which I moved to a different subwindow, are now moved back, or my stripes get removed and all curves from this plot are now plotted again in the same stripe.

Is there a possibility that the stripes and subwindows are retained when a new simulation is performed?

Thanks in advance

Lukas

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modgen: best way to change device m-factor?

March 9, 2018, 10:21 am
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Hello,

The following question does not have a clear answer for me after reading some of the Cadence documentation on modgen. I have been using modgen only recently and find it very useful, but wondered about the following case. I believe you have to be using IC 6.1.7 to even see modgen:

Q: I have created a modgen in Schematic-XL and placed the devices how I want to in the Modgen layout editor through Module Generator. After saving and closing all of this, I later realize I want to change an NFET from m=2 to m=4. What is the best way to make this change?

Main problem I see is not having a simple way in Schematic-XL to update in the constraint manager the specific device I changed, so that the two additional devices (now m=4) show up within the modgen group. For example, if constraint manager showed Modgen(12) because I had 12 devices grouped, it should become Modgen(14) after I increase the m=2 to m=4. The "update constraints from layout/schematic" options do not seem to do anything.

What I've had to do is delete the original m=2 devices from the modgen constraint group, then add the m=4 devices back into the modgen group. But then sometimes when I open Modgen Layout Editor it resets the positions of all the devices I had placed before the change. I've tried making the schematic change only after I've had the Modgen Layout Editor open as well, but it doesn't work as smoothly either. It also isn't clear to me in which cases I use the "update all schematic constraints from layout" or "update all layout constraints from schematic" commands.

Does anyone have any suggestions on how to best modify an instance's m-factor after having already performed the layout placements in a modgen? And so placement doesn't reset?

Thanks,

af

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*WARNING* Connection to MACHINE failed. No route to host

March 10, 2018, 6:20 pm
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Hello,

when I want to start PVS in the Virtoso Layout Editor I get the warning *WARNING* Connection to MACHINE failed. No route to host in the CW. (MACHINE=name of the machine on which I started Virtuoso). When I start PVS standalone (from the terminal) everything works pretty fine.

How can I get more detailed information on what causes this warning?

Kind regards,

Matthias

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RE: Electromigration SEB flow FIT calculation

March 12, 2018, 5:16 am
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Hi All,

Heard about SEB(Statistical EM Budgeting) flow to measure FIT(Fails in Time) for interconnects. It includes joule heating of inter connects as well as self-heating. Anyone know how to do this in spectre ADEL/XL EMIR analysis? Any references to do it? I have gone through the manuals and couldn't find anything regarding FIT. Is it possible in ADEL/XL.

Thanks.

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Virtuoso XL: Pins are preventing Analog Adjust Cell Sides from adjusting PRBoundary correctly

March 12, 2018, 8:26 am
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I'm currently using Virtuoso XL version IC6.1.7-64b.500.6 to do custom analog layout.  I'm fairly new to IC6, and I do not have any corresponding Cadence schematics for my layout.

I have three pins named VCCOK, VCCEXT, and BGGND respectively.  Note, these are signal pins in this design, not power rails. 

When I use the "Analog Adjust Cell Sides" feature, VXL moves these three pins to the top and bottom of the layout cell, but outside the cell extent for any other active area devices.  It them wraps the cell with PRBoundary.  The problem is, VXL places these pins so that the PRBoundary is then a pin's width larger than it should be on both the top and bottom of the cell.  VXL also changes the placement status of these pins to "Placed" automatically.  The default placement status of all pins is always set to "none" here.

If I manually set the placement status on these pins to "Fixed" or "Locked/Cover", the Analog Adjust Cell Sides tool does nothing, and refuses to adjust the PRBoundary.  If I manually set the placement status on these pins to "Placed", the Analog Adjust Cell Sides tool ignores the setting, and moves them as if they were set to "None".

I'm guessing that due to each pin having either a "VCC" or "GND" somewhere in the name, the tool is automatically assuming these are power rails, and not just normal signal pins.

Is there a way to stop Analog Adjust Cell Sides from moving the above named pins differently than it handles regular IO pins?

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Getting started with modgen

March 13, 2018, 7:48 am
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I am trying to get started with modgen. A friend of mine gave me some information provided by him but it refers to an old version which is quite different from mine. Do you know where can I find some instruction on how to get started with this new version? Briefly, I want to use it for placing/inter-digitation/dummy-generation. My current Cadence Version is:  IC6.1.6.64b.500.6

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Two Pins on the one wire

March 13, 2018, 9:16 am
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Is there a way to place two pins on a wire without creating a short?

I'm trying to make a four port transformer PCell.

Each winding is just a metal path and I can't see how to have input and output pins for each path without causing a short.

In a previous project I used metal resistors to break up the wires but that was time consuming and wouldn't be process independent.

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Preventing the config view from defaulting to AMS

March 15, 2018, 9:10 am
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When I load the config view it defaults to the AMS simulator and not spectre.

I've set the environment variable "asimenv.startup simulator" to spectre but the config view overrides it, is there a way of stopping it?

From the docs

>Sets the default simulator for the Analog Design Environment.

>To set this variable in the .cdsinit file or CIW, use the following call:
>envSetVal("asimenv.startup" "simulator" 'string "simulatorName|auto")

>When this variable is set to auto:
>AMS is set as the default simulator if the view is a config view and it includes Verilog views, which are any text views like .vams, .sv, .v, and so on.
 >Spectre is set as the default simulator if the view is not a config view or it does not include Verilog views.

I haven't set it to auto though and this still happens.

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how to customize right click menu in adexl data view window and add save option

March 16, 2018, 4:07 am
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Hi,

    I am using adexl to run analog design. In general, there are many functions in the right click menu in the data view window, when you right click your test name. At the same time, I find the output save option is not included in this menu, and I have to open ade L editor to edit such saving signals and save option every time. 

    Is there any way to add&customize saving option to right click menu ? 

BR

Thanks

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Parameterization feature of ADE-XL does not work with Schematic Pcells

March 16, 2018, 7:07 am
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Hello, 

I am using  ICADV12.3-64b.500.17 

and I am trying to parametrize a design using the variables and parameters window in ADE-XL, and I am facing two different issues

I noticed that sweeping some parameters simply didn't work, by investigating the netlist I saw that although the swept parameters are set correctly at the begining of the netlist it is not passed to the device instant, in my case this problem was specific to schematic Pcells (ex. a Pcell which generates stacked devices) , so when sweeping the parameter number_of_series_devices in the PCell the structure of the underlying schematic needs to be re-evaluated but this is not happening 

additionally, I noticed in general that any parameter which is modified in the parent schematic Pcell is not passed to the underlying Pcell even if it is not affecting the structure 

Thanks 

Fahmy

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