Hello,
I defined in Library Manager -> Edit -> Display Settings, some custom settings.
How could I change them? Is there an editable configuration file in which they are saved?
Thank you
Best regards,
Aldo
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Library Manager display settings
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line continuation symbol for the cds.lib file
Hello,
is there a line continuation symbol for the cds.lib file?
Thank you,
Aldo
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How to find frequency for ring oscillator in Monte-Carlo analysis?
Hi
How to find frequency for ring oscillator in Monte-Carlo analysis?
thanks
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Virtuoso ADE Explorer/Assembler problem with load balancing system (type SGE)
Dear All,
I have come across problem when trying to run jobs over load balancing system of SGE type while using Virtuoso ADE Explorer and/or Assembler (IC_6.1.7.715 aka IC6.1.7-64b.500.15). I have no problems when it comes to older tools like ADE-XL. I had spent some time to debug it and by exploring inside of the farm node I have found out that :
1) if spectre job to be excuted is of single point (no parameter scans etc), then it does it on the farm node via axlGenerixGlobalLauncher script which calls runSimulation script - and all goes ok.
2) if job is of multipoints then as usual it uses runICRPxx script that launches nograph virtuoso which in normal conditions should start simulator via runSimulation script. However.. instead - it tries to launch simulator back on the submission host (!) via cdsRemshClient call. Here is the output of 'ps' command run over farm node farm036:
[root@farm036 ~]# ps uaxwwf | grep user
root 21420 0.0 0.0 9044 664 pts/0 S+ 17:34 0:00 \_ grep --color=auto user
user 17608 0.0 0.0 22076 1712 ? Ss 17:31 0:00 \_ -sh /opt/sge/default/spool/farm036/job_scripts/42280
user 17649 0.0 0.0 9528 1344 ? S 17:31 0:00 \_ /bin/sh /projects/PDK/SigmaDelta/V1.0/workAreas/user/.tmp_user/.cmddir0/runICRP0
user 17688 3.7 0.7 1452752 467976 ? S 17:31 0:05 \_ /eda/cadence/2017-18/RHELx86/IC_6.1.7.715/tools.lnx86/dfII/bin/64bit/virtuoso -noautostart -mpssession virtuoso11005 -mpshost work053 -davinciService DaVinciService_11005_1519057891 -log /projects/PDK/SigmaDelta/V1.0/workAreas/user/logs_user/logs0/Job0.log -licenseLockFileName /projects/PDK/SigmaDelta/V1.0/workAreas/user/.tmp_user/.work053_11005 -nograph -nostdin -axlChildIdFlag 0
user 21410 0.0 0.0 2460 708 ? S 17:34 0:00 \_ /eda/cadence/2017-18/RHELx86/IC_6.1.7.715/tools/bin/32bit/cdsRemshClient work053 -cdsPath tools/bin/cdsServIpc -s farm036 -c 47686 -n 1 -r 0 -x cd /simulation/user/ResDir/testWB/testInverterTB/maestro/results/maestro/ExplorerRun.0/1/testWB:testInverterTB:1/netlist ; ./runSimulation
user 21418 0.0 0.0 0 0 ? Z 17:34 0:00 \_ [cdsRemote.scr] <defunct>
where work053 is the submission host (where main ADE Explorer is run) and farm036 is the farm node.
so far I have cut .cdsinit init to the minimum and tried:
;; forcing distributed mode to NOT copy files into exec machine:
envSetVal("asimenv.distributed" "copyMode" 'boolean nil)
;; disabling interactive ADE Assembler and Explorer modes:
envSetVal("maestro.simulation" "interactiveE" 'boolean nil)
envSetVal("maestro.simulation" "interactiveA" 'boolean nil)
;; forcing to use ssh in remote shell calls:
envSetVal("asimenv.distributed" "remoteShell" 'string "ssh")
;; helpers for debugging ADE-XL/Assebler :
(when (axlIsICRPProcess)
_axlDebugTimeFlag = t
(sstatus errsetTrace t)
_stacktrace = 50
;_axlCallbkDebugFlag = t ;uncomment this if debugging callbacks
)
;; make stdout and stderr visible
(envSetVal "adexl.icrpStartup" "showJobStdout" 'boolean t)
(envSetVal "adexl.icrpStartup" "showJobStderr" 'boolean t)
and set env. variable AXL_PEJM_DEBUG=3 as suggested in one of trouble shutting articles on the KB.
As I had mentioned above - I have no problem with job executions over SGE farm while using ADE-XL tool.
Any ideas ?
Wojciech
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not_gate verilogA model in ahdlLib
The following lines are in the verilogA model of "not_gate" in ahdlLib. I have marked 3 lines as A, B, C.
@ ( initial_step ) begin
... <<deleted lines>>
end
logic_in = V(vin) > vtrans; // line A
@ (cross(V(vin) - vtrans, 1)) logic_in = 1; // line B
@ (cross(V(vin) - vtrans, -1)) logic_in = 0; // line C
- What is the reason for having both line A and lines (B,C)? Latter seem to imply the former unless the inputs don't cross the threshold at all during the transient simulation.
- Would it have been enough to have line A within @(initial_step) begin ... end?
- If line A is indeed redundant, does having it slow things down because it is continuously evaluated?
Other gates have similar codes.
Thanks
Nagendra
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filter_sg in dyn_floatdcpath check
Hello All,
I was exploring dyn_floatdcpath check in spectre. Came across a filter , filter_sg. But couldn't make it work at all. Any suggestions on how to use this filter?
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Parametric Analysis - Random Values
Hi Friends,
In the ADE L - parametric analysis, I could see options to sweep the variable in the linear/logarithmic/auto etc between the specified min and max values. But is there any option to provide random values to the variable. So I would like to vary the parameter randomly within the min and max values and see the performance of the circuit. Kindly provide your suggestion.
Thanks in advance
Regards,
Vijay
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VerilogA model Monte Carlo Simulation - Histogram Curve
Hi,
I want to try monte carlo analysis for circuits defined in veriloga model. So I have started with the ahdlLib" "res" cell example provided in the cadence support ((Link) . I have done the following steps to replicate the procedure.
- Modified the verilogA model of "res" cell from ahdlib library as given in the example
module res(vp, vn);
inout vp, vn;
electrical vp, vn;
(* cds_inherited_parameter *) parameter real monteres = 0;
parameter real r = 1k;
localparam real r_effective = r + monteres; // nominal resistance plus
// monte-carlo mismatch effect
analog
V(vp, vn) <+ (r_effective)*I(vp, vn);
endmodule- Created res_mismatch.scs file with the following content
simulator lang=spectre
global 0
parameters monteres=10
statistics {
mismatch {
vary monteres dist=gauss std=5
}
}
- Created schematic with the modified res cell and vdc source
- Added the model file (res_mismatch.scs) in the ADE L environment and executed transient simulation. Its working fine.
- As I want to see how my circuit (vdc connected to res cell) current varies with respect to resistance variations using monte carlo simulation, I setup ADE XL environment and configured the test.
- Selected the monte carlo sampling and selected the mismatch statistical variation with number of points as 10
Simulation was completed without any error. But I am not able to get any histogram curve or distribution curve. I want to plot the histogram of circuit current variations with respect to resistance mismatch characteristics.
I think, I am missing few more steps. Kindly help me to get it.
Regards,
Vijay
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Inconsistent "PSD" results between MATLAB & Cadence Calculator
Hi all,
I have been trying to verify the variance (total power) of a random normal distributed noise source.
The noise source model has been modified from the noise_src in ahdlLib but with $rdist_normal() rather than $random()/`MAXINT
V(vout) <+ amp*$rdist_normal(seed,0,1);
where amp is exactly one sigma in normal distribution case.
In this example I give amp = 100u and the resulting output random signal is shown below:
I used to dump this signal to MATLAB and do the FFT & PSD calculations based on the script described in this website:
"Power Spectral Density Estimates Using FFT"
www.mathworks.com/.../power-spectral-density-estimates-using-fft.html
Take nfft = 65536, sampling time = 1/1GHz.
The resulting integral of the overall spectrum is EXACTLY equal to sigma^2 = (100u)^2.
The PSD setup in VIVA Calculator and the result are shown as follows:
Then I apply iinteg to the PSD and take square root, and the integrated value at the final data point (0.5*sampling frequency) is expected to be sigma=100u.
However, the outcome seems to be smaller than what is expected. ( (82u-100u)/100u ~ -18% error)
There is still a constant -18% error no matter what sigma value I give.
I also ran transient noise simulation with the resistor model given in analogLib to verify that 4kTR*NoiseFmax = sigma^2.
Again, there is a -18% gap between VIVA calculator PSD function and MATLAB PSD.
If I extract the PSD data from VIVA calculator and do integration in MATLAB, the result is identical to that done in VIVA calculator. (-18% sigma)
Based on the trials given above, I suspect the algorithm of PSD function in VIVA calculator is not what I expect to be.
Can someone help me clarify this problem?
Thanks a lot :)
Version Information
virtuoso 6.1.7-64b
spectre 16.1.0 32b
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Techno via construction constraint for overlapping vias
Is there a via constraint supporting following DRC rule: Minimum extension of Mx beyond the overlap area that VIAx and VIAx-1 are fully or partially touching.
So the metal extension must be larger larger when 2 vias are stacked.
Thanks,
Rik
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How to set conditional tests in ADEXL to avoid running tests not needed in a sequence of tests.
Hello All,
I am currently executing a pre-trim and pos-trim checks for an oscillator using ADEXL and Montecarlo sampling with the PSS tool. In the initial pre-trim I ran the simulation bench at 27degC and find a gross code approximation. Then in several post-trim simulations I refined the search to obtain the best code. I used a combination of "calcVal" and "VAR" to share information between the consecutive tests. The problem is that I am spending like 5 tests to find the best code even if in my first test I already found the best code. I would like to find a way to not enable the next tests if I already found the code in the first tests. Something like a conditional that if the error is less than half the LSB I would not run the next post-trim tests and I would run just the last two tests, that are actually at a different temperature sharing just the best code found in the first tests.
The sequence I follow is:
1) Run test at 27 degC and find the approximated code to center the frequency of the oscillator.
2) Run same test at 27degC with the code found in 1). Measure frequency and find a better code than in 1).
3) Run same test at 27degC with the code found in 2). Measure frequency and find a better code than in 2).
4) Run same test at 27degC with the code found in 3). Measure frequency and find a better code than in 3).
5) Run same test at 27degC with the code found in 4). Measure frequency and find a better code than in 4).
6) Run same test at 27degC with the code found in 5).
7) Run same test at -40degC with the code found in 5).
8) Run same test at 125degC with the code found in 5).
If the error during any of the steps 2) to 5) is less than the desired accuracy do not execute more tests at 27degC and jump directly to tests 7) and 8) saving the best code found in that specific test.
I already have this sequence working from 1) to 8) but I would like to save tests if they are not needed.
Thanks a lot for any help you can give me.
angel
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error in checking lvs test with calibre tool
hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors .the problem is when i try to check lvs it gives me an error as following :
no matching ".SUBCKT" statement for "SPIRAL_STD" what should i do to solve this i already read some forums that i added below but still didn't figure out what to do. thanks in advance.
community.cadence.com/.../tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade
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more pin name and net name checking at check and save
Hi,
How to add in more custom checking during the check and save? For example, we would like to forbid some specific keywords (say, verilog keywords in a list file) for pin names or even wire/net names. By doing that, we can avoid analog designers using some digital keywords which might cause some potential unnecessary issues.
The whole idea might be like this: at the check and save, a skill would be triggered to load the list and check against it.
Thanks.
Andrew
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Leakage current and Leakage power
Hello,
I'm designing an SRAM cell for my project using 45nm technology.
I would like to calculate the leakage current and the leakage power. Could anyone elaborate the steps that I need to follow?
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Verilog-A model and temperature in AC-Sim
I have a verilog-a model that is dependent on the simulation temperature, using the "$temperature" variable.
The temperature value changes vs. corner simulations. The simple model gives a voltage in dependence on the temperature.
The following code works:
analog begin
V(out,vss) <+ $temperature-273.15*V(in,vss); //Input voltage is always 1V
end
This code does always give me 27 degC:
real temp_degC = 27;
analog begin
temp_degC = $temperature-273.15;
V(out,vss) <+ temp_degC*V(in,vss); //Input voltage is always 1V
end
Why is that and how can I make the model evaluating the "temp_degC" correctly ?
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MonteCarlo simulation is taking much longer time than expected
Dear All,
I am simulating Monte-carlo of 100 runs on a test-bench with PSS/PAC analysis.
The standalone PSS/PAC run takes just 30 seconds.
But when I run with Monte-carlo, it is taking much longer time than expected. Each run is taking more than 5 minutes.
More interestingly, as the run number increases, the time increases further. For example, the run#5 took 2 minutes. Now the run#45 is taking 12 minutes.
Why this is happening like this ? I have disabled Montecarlo data Save and Plot save.
Could anybody please tell how to get rid of this issue ?
My Virtuoso and Spectre versions are below:-
virtuoso -W
sub-version IC6.1.6-64b.500.14
spectre -W
sub-version 14.1.0.988.isr20
Kind Regards,
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Veriloga parameter expression
In veriloga documentation I have seen examples where one parameter is used to set the default of another parameter in the same module.
When I tried this I found it didn't work in ADE/spectre. A simple example:
==============================
`include "constants.vams"
`include "disciplines.vams"
module test_param(n1, n2);
inout n1, n2;
electrical n1, n2;
parameter real myres = 1k;
parameter real twores = 2*myres;
analog begin
I(n1, n2) <+ V(n1, n2)/twores;
end
endmodule
========================
When I tried simulating this in a test bench, ADE added myres to the list of design variables to be set.
If I try running without setting a value I get an error:
Error found by spectre during hierarchy flattening.
ERROR (SFE-1997): "input.scs" 14: I0: parameter `twores': Cannot run the simulation because parameter 'myres' has been used but no value has been assigned to it. Assign a value to the parameter and rerun the simulation.
Is this a bug?
Thanks,
Robin
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ADE XL netlisting error (some schematic components are blank)
I have a simulation that isn't working with ADE XL - whenever it netlists parts of the netlist have no connections. I am using standard cells with predefined connections in them and have some schematic parts that are made with symbols for the objects (standard cells) but the netlists created with those parts are empty. Some parts only have the instance names, no connections, and other parts are fully defined. Are there any options I should be looking into?
Thanks
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Color of "tool tip" text
Hi,
I seem to have inadvertently changed the color of the text of the "tool tip" (the bubble that shows up when you hover your mouse over a button in the GUI, for example when you hover your mouse over the green "Play" button in ADE-XL). The color of the text is black by default and it's changed to white (really difficult to read with the pink background of the bubble!). Where can I set this text color back to the default black? I'm using Virtuoso 6.1.7.
I'm assuming it's set somewhere in the cdsinit or cdsenv file but I can't figure out how to change this
Thanks,
Shaan
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Converting Waveform data to list or vector using ocean Script
Hello,
I am using "cross function" on the output waveform in cadence which is giving me a 2D vector( Multiple rows and 2 columns).
wave=cross(v("/OUT" ?result "tran") 0.6 1 "either" t "time" )
I want to print the result in a file in two different vectors using script. SO, that i would be able to access the individual element of the vector.
There is already ocean script online but it is not working for my case.
I would be really grateful, if you would be able to help me with the solution.
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