How to Save Optimized Design Variables to a new Corner for Later Simulation

January 25, 2018, 2:24 pm

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Hi 

I am running ICADV12.1.500.152. The spectre version is 15.10.602 sub-version 15.1.0.602.isr11.

I am running ADE-GXL Global Optimization to find optimal setting of a control variable to achieve a specified outcome (say output impedance). I am needing to optimize this design variable across PVT. Once the optimal setting has been found for each PVT condition, I'd like to capture the variable setting  along with the various PVT conditions as a corner, sort of like creating a corner from a monte carlo design point. These corners will be used for subsequent simulations with the optimized design variables dialed in for each PVT situation.  I have tried the "Create Copy of Selected Corner"  by right clicking in the optimized setting column in the Results window,  but that does not create the corner with the design variable included.

The current work around is to run the optimization then create the corners by hand from writing the results to csv files and post processing the data to back annotate to a corners.csv file, but this is tedious.

Any help would be appreciated,

Justin

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Parameter passing hygiene

January 25, 2018, 6:33 pm

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I'm trying to make a parent schematic/symbol wrapper cell around a confusing looking child cell that has parameters e.g. a, b, c and displays those parameters via labels on its symbol. Note also that entering the parameters on the child passes them into some code via callbacks. All parameters are text fields.

I want my wrapper cell to have exactly the same parameter names and just pass them down to the confusing child cell, so I create parameters a, b, c on the parent and in the child cell I set it's parameters to [@a], [@b] and [@c].

I have two problems:

1. Because the parameter names are identical for the parent and child, I seem to be getting an illegal loop when in the child cell I set parameter "a" to "[@a]". I really want the parameter names to be the same on both the parent and child cells. How would I do this?

2. When I enter the parameters on the parent (e.g. set a to 1, b to 2, c to 3) and then descend in to reveal the child cell, the child symbol parameter labels aren't showing 1, 2 and 3 - they're showing [@a], [@b] and [@c]. How can I have the child symbol show be the actual values passed down from above? Remember, the child cell operates on its parameters via callbacks and the callback is receiving “[@parent_param]” or “pPar(\“parent_param\”)” depending on what I've tried so far.

I'd really appreciate some help on this and I'm sure this is a silly newbie question, so apologies in advance.

calibre results directory

January 26, 2018, 2:48 am

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Hi to everybody,

I have the need to change the directory where the calibre results are saved. For the simulations, I use the following in my cdsinit file:

envSetVal("asimenv.startup" "projectDir" 'string "MY_SIMULATION_DIRECTORY")

Should I do the same for calibre? For example the following line?

envSetVal("asimenv.startup" "projectDir" 'string "MY_CALIBRE_DIRECTORY")

Thank you in advance

Nicola

cadence chip assembly autorouter drc error

January 28, 2018, 3:17 pm

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Hi,

I am using cadence version IC6.1.6 to design in soi45nm technology. I have a drc rule file to be used with calibre nmDRC but it does not support assura. When I tried to run chip assembly router for automatic routing, there were many drc errors on the finished layout. I am guessing it might be because virtuoso chip assembly router uses default design rule file and therefore not consistent with the rules used by calibre. 

Can anybody offer any insight into this. What should be the approach to convert calibre drc rule set to assura so that I can run assura drc or is there other way to get around this problem. I am also thinking if it would be possible to guide the auto router to use calibre drc rules. 

So far I know that my university does not have assura drc rule file for soi45nm technology. 

Thanks

Supriyo

VAR syntax in Digital Vector File

January 30, 2018, 6:16 pm

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Hi,

I am trying to simulate a circuit with different input patterns in ADE-XL. I have created several input patterns in separate VEC files. However, I am unable to use the VAR syntax which will allow me to choose which VEC file to simulate using a variable. Appreciate it if could share a way to enable the VAR syntax or suggest a workaround.

Thank you!

How to import verilog code into virtuoso?

January 31, 2018, 3:35 am

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I have a sequence detector verilog code. I want to import it into cadence virtuoso and simulate it along with my other circuits. 

I am using the Virtuoso custom ic design environment version IC6.1.6-64b.500.14.

I have checked some online guides and manuals to do this but somehow I always end up with errors. Is there an correct method to do this? Because the online manuals are for different version of virtuoso. 

Switch View List in Virtuoso CDL Out ignored?

February 1, 2018, 6:14 am

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I was trying to export a CDL netlist from virtuoso (IC617) with File->Export->CDL in the CIW.  In the "Virtuoso CDL Out" form, I filled out the "Switch View List" field with "auCdl schematic cmos_sch" (by adding cmos_sch to the end).  However, when I hit apply, the netlisting fails and the error is

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'auCdl schematic', for the
instance 'I3' in cell 'MYCELL'. Add one of these views to the cell 'MYSTDCELL' in the
library 'MYSTDCELL_LIB', or modify the view list so that it contains an existing view.

(cell/lib name changed)

So, what gives?  The view list in the error is not the view list I put in the form.   When I looked at the si.env file which got created, I see:

simViewList = '("auCdl" "schematic" "cmos_sch")
simStopList = '("auCdl")

if I manually edit this file and add

cdlSimStopList = '( "auCdl" )
cdlSimViewList = '( "auCdl" "schematic" "cmos_sch")

and run

si -batch -command netlist

from the command line I'm able to netlist.  I do not have a .simrc file anywhere that I can find which might be messing with things.

Any thoughts?

Thanks

-Dan

A file needs to know it's place in the world

February 2, 2018, 7:33 am

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I have a file that contains skill code that can modify it's behavior based in where it exists within the file system. Is there a way for the file to determine the name of its unix parent folder?

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Display problem when I zoom in multiple waveforms

February 5, 2018, 2:52 pm

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I have some waveforms to be plotted. Before zoom in it, the waveforms look good:

However, when I zoom in it, we can see that the waveforms are totally wrong because they should be straight with reasonable delays:

The correct waveforms can be displayed when I select them:

As we can see from the above figure, both correct and wrong waveforms are plotted together. This troubles me for a long time because usually I need to zoom in waveforms and see the relationship of some waveforms. The existing of wrong waveforms always disturb my judgement.

Thank you.

How do you right justify multi-line labels?

February 5, 2018, 8:14 pm

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I have a 2-line instance label that I've created by extracting various attributes from the cell via some skill code. I don't want to break the 2-line label up into 2 separate 1-line labels, and each line can be a random length. If I take the label and give it a justification then only the box containing the 2 lines of text receives the justification, but the text inside the label's bounding box is always left justified. I want the text inside the bounding box to be right justified. How do I do this?

Menu Assura only in windows Layout not present in the window Schematic

February 5, 2018, 11:45 pm

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Hi, All.

I noted that menu Assura only in windows Layout and not present in the windows Schematic.

I think menu Assura should also be in the Schematic window? Or I am mistaken?

Are inherited connections supported by layout XL

February 6, 2018, 1:37 am

≫ Next: RC Extraction Problem with GPDK045

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Hello,

I have a problem with inherited connections of the schematic. I have an inverter using an inherited connection for vdd and vss. The correct netname is assigned by setting a user property. This assigned netname however is not propagated to the layout. The CDL netlist generated from the schematic is correct, so it looks like the problem is only with XL.

In layout the generic net name is assigned to the pin (e.g. VDD_33!).

Is there something wrong wrong, or is it just not supported?

RC Extraction Problem with GPDK045

February 6, 2018, 6:55 pm

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Hi All, 

I am working with Cadence provided GPDK045 technology. Our course admin has installed the latest version of it (Aug 2017). Still the PDK has bugs and cannot run very basic functionality like RCX extraction.  

Some user also faced exactly the same error 2 years ago. The solution recommended then was to download the latest gpdk045 kit. I am not sure if it fixed the error for that user, but definitely this error still persist in the PDK available as of Aug 2017. 

 Kindly advice what can I do. It is bit urgent to resolve this issue. 

********************************************************************************************

*** ASSURA capgen VERSION 3.2 Red Hat Linux release 7.2 (Enigma) - (07/07/2010-10:53) ***

**********************************************************************
*WARNING* at "capgen": process layer 'FOX' maps to one or more extraction
layers that do not appear in the lvsfile.
*WARNING* at "capgen": Substrate layer 'FOX' will be automatically generated
during extraction due to incomplete p2lvs mapping. This may lead to
unintended results.
*ERROR* at "capgen": -cap_ground_layer 'psubstrate' not defined in LVS file
quitting.
Forking: /share/instsww/cadence/ASSURA41-615/tools/assura/bin/64bit/capgen -techdir /home/gpdk/gpdk045/assura/../qrc/typical -lvs /home/cadence/DRC_LVS_sims/inverter.xcn -p2lvs /home/gpdk/gpdk045/assura/../qrc/typical/p2lvsfile -p poly_conn,allGate,Oxide -canonical_res_caps -length_units meters -exclude_gate_res -cap_ground_layer psubstrate /home/cadence/DRC_LVS_sims/inverter
*WARNING* Bad return status from RCX script generator. 0x100

LVS fails "nothing in layout"

February 7, 2018, 1:59 am

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Hi all,

I can't solve this problem with LVS while trying to do the following:

I have two MOM caps that I made by myself (in the pcell that I have I can't set the dimensions that I want), shown in the first picture. In this case the LVS recognizes them as MOM caps, meaning that my layout of each of them is correct. However, if I overlap them like in the second picture (I do this because they will have a branch in common), I get the error in the title, so they are not recognized anymore as correct pcells. I also tried to make a group for each of the two MOM cap, but the LVS still doesn't recognize anything.

Do you have a solution to perform my task?

Thank you in advance,

Nicola

Including dspf file in Spectre and back-annotation of transistor's parameters and fingers

February 8, 2018, 12:36 am

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Hi,

Up until now, we were either using calibre/extracted view or included dspf file as a regular netlist.

Due to issues with both approaches (large dspf with wrong pin order), we want to check using DSPF back-annotation.

From the documentation, it quite clear that by default, Spectre does back-annotates transistor's parameters from the instance section of the DSPF file, however, it is not clear how it handles transistors fingers and multiply:

• Does Spectre recognizes the cases where transistors in DSPG are split due to fingers or m factor?
• If it does, how does it handle this case? Does it internally split the transistor or does it combine them back the single transistor statements with all RC between the pins shorted?

Thanks,

Ronen

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Require Help regarding adding custom layer/extraction in GPDK45nm

February 11, 2018, 8:02 am

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Hi All, 

I am using gpdk 45nm & require some help regarding adding custom OXIDE  layer in Virtuoso layer  (say COXIDE). I am able to add custom layer in the layer pallete and draw it. But i have the below queries. 

1) How can i set the sheet resistance / capacitance values for the layer  and use the values in actual layout ? 

2) How do i query the above properties once set ? 

3) Can i do extraction and dump spice netlists for poly-COXIDE-poly ? 

4) Can i dump all required views for the poly-COXIDE-poly - like spectre / ivpcell / hspiceD ?  (i.e all the views other predefined cell has) 

Thanks & Regards,

Ryan_IITD

Virtuoso XL LE: Extract connectivity through "empty" areas

February 12, 2018, 2:36 am

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In layout XL, there are layers defined that are electrically connected. However, in most technology, the substrate is just empty area.

So is there a way to set up the techno so this empty areas are electrically connected? For example, everything that is not NWELL, is PSUB, and must connect to P+ diffusion.

Monte Carlo Design Variables?

February 13, 2018, 1:49 pm

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I would like to run a monte carlo simulation in ADE-XL (well, actually I want to run in Ocean-L but that is no longer supported) where some of my design variables have variation.

I tried as an example, instantiating an analogLib/vdc voltage source with dc=MYVDD.  Then I put in MYVDD=1 in the design variables list.

Then I created a spectre model file that included:

parameters my_vdd_mc=1

statistics {

  process {

    vary my_vdd_mc dist=unif N=0.2

  }

}

my_alter_vdd alter param=MYVDD value=my_vdd_mc

and included this in my model setup.  I picked all (process+mismatch) for the simulation but the simulated (monte carlo) voltage is rock solid at 1.0V, no variation at all.  Looking at input.scs and spectre.out it is clear what the issue is.  The alter commands are *outside* of the monte carlo loop instead of inside it which isn't all that surprising.  Ok, so how to fix that?

I tried directly using dc=my_vdd_mc in the test bench schematic (i.e. skip the alter statements).  Now ADE-XL freaks out because it says "hey, you are trying to use my_vdd_mc but I don't know anything about it".  Yes, I know ADE-XL doesn't know anything about it, the model file I created adds it.

So... I guess my next approach will be to create a cell "my_supplies" that has a symbol and spectre view and then put the voltage source in the model file as well.  However, this seems like a pain and gives less flexibility, especially if I needed to use the statistically varying variable in multiple spots.

Is there anyway to tell ADE-XL to cut me some slack on defining a parameter in a model file instead of via the GUI? 

Thanks

-Dan

VHDL AMS and LTF

February 14, 2018, 5:59 am

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Hi,

I'm trying to simulate a simple opamp model which is written in VHDL AMS. Unfortunatly the AMS Simulator does not simulate it and produces the following error:

Analog Kernel using -ANALOGCONTROL  ./amsControlSpectre.scs.
Reading file:
        /.../netlist/amsControlSpectre.scs
ncsim: *E,EUNLTF: /.../vhdl.vhms:101: vin'LTF_101_15: The parameters of the LTF attribute must be aggregates of scalars.

Error found by spectre during circuit read-in.
    ERROR (SPECTRE-357): AMS Analog Elaboration has exited with error.
        Simulation will terminate.

The corresponding part of the model looks as follows (wP1, wP2 and gain are real generics):

constant num : real_vector := (0 => wP1 * wP2 * gain);
constant den : real_vector := (wP1 * wP2, wP1 + wP2, 1.0);
vout == vin'ltf(num, den);

Are their any ideas in how to resolve this error?

customizing ViVA result browser traces default settings

February 16, 2018, 5:41 am

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Hi,

when the result browsre opens after a Simulation, all traces are "combined" in one graph.

I would like to change the default settings, so that the traces are shown as "split strips" automatically.

I found a solution in the forum thread "customize viva Strip", but this does not work in my case, and I do not know why.

I tried both, the .cdsinit and .ecdenv commands.

I am using virtuoso 6.1.7.500.14.

Any idea ?