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Queue list in job policies of ADE

January 12, 2018, 12:43 am
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Hello All,

Under the job setup in ADE, there is a drop down under "queues" where I can select the available LSF queues. Earlier I was able to see "normal , regress, hwsim" . Now only normal is showing up there.

I got a workaround using the "asimenv.distributed" "queueNameInclusionList" variable and setting it. 

I have checked "queueNameExclusionList" also. It was empty.

Since many users are facing similar issue here, I want to find the root cause for this.

Any one knows, from were these queue names are picking up? I have checked .cdsinit,.cdsenv for any environment variables, but couldn't find any.

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Number of accepted tran steps in spectre log

January 12, 2018, 1:10 am
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When a transient analysis in spectre is done, in the log file there is a statement " Number of accepted tran steps" . And it shows a big number. However in the statements above, a very few number of tran points are shown. What is the significance of these points.?

In diagnostic mode, when +transteps is used, all these points are showing in the log file

.

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variable $freq in veriloga

January 12, 2018, 11:57 am
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Can use $freq in veriloga if I want to create an expression for say a frequency dependent gain in AC analysis?

I gave this a try but so far it hasn't worked but the veriloga compiler and the spectre aps linter haven't complained either.

Thanks,

Robin

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[IC6.1.7] Simulating VHDL-AMS

January 15, 2018, 3:43 am
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I am trying to perform a simple simulation with a VHDL-AMS modeled resistor. Unfortunately I cannot simulate it.

I made the following:

  1. Created a new Cell View in the Library Manager with the type VHDLAMSText
  2. Added the VHDL-AMS Code to the file and saved it via File->Extract
  3. Created a symbol for the resistor (resp. Virtuoso created that automatically)
  4. Created a new Cell View in the Library Manager with the type schematic
  5. Added a simple test circuit in the schematic (One source and my resistor)
  6. Switched to the simulator and added "ideal" to the Switch View List in the Environment options
  7. Tried to create the netlist Simulation->Netlist->Create

Unfortunately the following error occurs:

Netlist Error: Cannot find any info on instance "I1" in cell-view "fh_hall_elements" "test" "schematic"
Netlist Error: Some cell-views used inside this block could not be netlisted in analog context

The element I1 is my resistor.

Any ideas on how to resolve this error?

Code of the resistor:

library ieee, std;
use ieee.std_logic_1164.all;
use ieee.electrical_systems.all;
use ieee.mechanical_systems.all;
use std.textio.all;


use ieee.math_real.all;

entity myres is
port (terminal p1, p2: electrical);
end entity myres;

architecture ideal of myres is
constant R : real := 10.0e3;
quantity v across i through p1 to p2;

begin
i == v/R;
end architecture ideal;

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What is the difference between the $PATH variables?

January 16, 2018, 2:53 am
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This applies to different instruments, but in the example of SPECTRE.
in bash environment $PATH variable is setting
1)
export MMSIMHOME=$CADHOME/SPECTRE16
export PATH=$PATH:$MMSIMHOME/tools/bin

2)
export MMSIMHOME=$CADHOME/SPECTRE16
export PATH=$PATH:$MMSIMHOME/bin

In both cases, everything seems to work.
But in the first case
.......
lrwxrwxrwx. 1 root root 22 Aug 15 11:12 spectre -> ../spectre/bin/spectre
lrwxrwxrwx. 1 root root 30 Aug 15 11:12 spectre_encrypt -> ../spectre/bin/spectre_encrypt
lrwxrwxrwx. 1 root root 27 Aug 15 11:12 spectre_root -> ../spectre/bin/spectre_root
lrwxrwxrwx. 1 root root 21 Aug 15 11:12 spectremdl -> ../mdl/bin/spectremdl
lrwxrwxrwx. 1 root root 28 Aug 15 11:12 spectreserver -> ../spectre/bin/spectreserver
lrwxrwxrwx. 1 root root 22 Aug 15 11:12 spfchecker -> ../emir/bin/spfchecker
lrwxrwxrwx. 1 root root 22 Aug 15 11:12 spicevisionpro -> ../SpiceVision/wrapper
lrwxrwxrwx. 1 root root 19 Aug 15 11:12 sptr -> ../spectre/bin/sptr
lrwxrwxrwx. 1 root root 21 Aug 15 11:12 tbl2macro -> ../emir/bin/tbl2macro
lrwxrwxrwx. 1 root root 20 Aug 15 11:12 temir -> ../spectre/bin/temir
lrwxrwxrwx. 1 root root 24 Aug 15 11:12 ultrasim -> ../ultrasim/bin/ultrasim
lrwxrwxrwx. 1 root root 26 Aug 15 11:12 ultrasim32 -> ../ultrasim/bin/ultrasim32
lrwxrwxrwx. 1 root root 26 Aug 15 11:12 ultrasim64 -> ../ultrasim/bin/ultrasim64
lrwxrwxrwx. 1 root root 24 Aug 15 11:12 uricheck -> ../relxpert/bin/uricheck
lrwxrwxrwx. 1 root root 24 Aug 15 11:12 usimEmirUtil -> ../emir/bin/usimEmirUtil
lrwxrwxrwx. 1 root root 26 Aug 15 11:12 usimEmirUtil32 -> ../emir/bin/usimEmirUtil32
lrwxrwxrwx. 1 root root 26 Aug 15 11:12 usimEmirUtil64 -> ../emir/bin/usimEmirUtil64
lrwxrwxrwx. 1 root root 27 Aug 15 11:12 usimtap2pti -> ../ultrasim/bin/usimtap2pti
lrwxrwxrwx. 1 root root 29 Aug 15 11:12 usimtap2pti32 -> ../ultrasim/bin/usimtap2pti32
lrwxrwxrwx. 1 root root 29 Aug 15 11:12 usimtap2pti64 -> ../ultrasim/bin/usimtap2pti64
lrwxrwxrwx. 1 root root 18 Aug 15 11:12 xps -> ../spectre/bin/xps
lrwxrwxrwx. 1 root root 19 Aug 15 11:12 xpss -> ../spectre/bin/xpss

In the second case, this is a link to only one file.
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spectre -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spectre_encrypt -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spectre_root -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spectremdl -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spectreserver -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spfchecker -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 spicevisionpro -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 sptr -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 28 Aug 15 11:12 srrversion -> ../share/dfII/bin/srrversion
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 tbl2macro -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 temir -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 ultrasim -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 ultrasim32 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 ultrasim64 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 uricheck -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimEmirUtil -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimEmirUtil32 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimEmirUtil64 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimtap2pti -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimtap2pti32 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 usimtap2pti64 -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 xps -> .cdnWrapperIndep
lrwxrwxrwx. 1 root root 16 Aug 15 11:12 xpss -> .cdnWrapperIndep

Which setting is more correct?

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Assura LVS Parameter Mismatch Error

January 16, 2018, 9:15 pm
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Hi All,

I'm using Virtuoso Layout XL 617 and Assura 415, with TSMC mixed-mode 130nm PDK.

I included a multi-fingered NMOS moscap into the layout, using the generated parameterized cell. The Cap has 5 fingers, W=L=20um for each, with top&bottom plate connection, and top poly contact head.

 

The cell looked like that above.

However, when running assura lvs, I got the following error:

Schematic Instance: C0 nmos1v
Layout Instance: avD10_1 N

w 2e-05 vs 0.0001 differs by 400%
Layout Instance is the merged result of: avD10_1 avD10_2 avD10_3 avD10_14
avD10_15

While clearly the device has five fingers totaling 100um, ASSURA says it's only 20um. It works only when just 1 finger is used. Is there an explanation to this weird behavior of ASSURA? Thank you very much. -Tony

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ADE XL Job Policy Setup -> Max. Jobs - automatic set after start

January 17, 2018, 4:55 am
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Default value Max.Jobs afte start always = 1


I saved setting via "Save Jobpolicy"


But the initial setting is still = 1.

What variable should I set in .cdsenv or load via .cdsinit for initial setting.

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How is the netlisting done in ADE

January 17, 2018, 10:20 pm
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Hello All,

How is the netlisting done generally.

I want to understand for example , an ams netlist will have instantiation of components in Verilog format. From where these ports for the models are picking up.

I can see in the model files for each component there are some parameters like length , width etc. In the netlist these are passed in Verilog format while instantiating that model using "analogmodel".

Thanks in advance

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noise analysis during transient

January 18, 2018, 2:20 am
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Hi to everybody,

I am running a noise analysis at a certain instant of time during the transient analysis; I do this using actimes and acnames features in the tran analysis options. The result I am interested in it's a value that I derive from the noise analysis, so, just a value (not a waveform). I am running corner simulations, and here comes my problem: the result of each corner it's a graph with only one point, so a value, but obviously I can't automatically see min and max values in the results window, but instead I have to read all the plots manually.

Why do I obtain a graph instead of a value? (if I don't use actimes and acnames I simply obtain a value). Thank you for the help,

Nicola

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Master file is missing from schematic

January 18, 2018, 7:27 am
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I am not able to open my schematic and symbol. It says Master file is missing but when I check it is there in folder but still complaining. Can anybody help me to resolve this issue?

Thank you 

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Parsevals theorem

January 18, 2018, 8:36 pm
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Hi,

I want to verify parsevals theorem in Cadence:

2.387E-3        stddev(v("/gnd" ?result "pss_td"))
2.387E-3        sqrt(integ(mag(v("/gnd" ?result "pss_td"))**2)/200e-9)
3.760E-3        sqrt(integ(mag(dft(v("/gnd" ?result "pss_td") 0 200n 2048 "Rectangular" 1 "default" 1.0 )/2048)**2))

The factor 3.76/2.387 is roughly pi/2 in which case I would accept it as some weird normalization. But not exactly. According to https://en.wikipedia.org/wiki/Parseval%27s_theorem my definition is valid.

What am I missing?

Thank you!

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need document regarding voltage sources and it usage (vdc, vpulse..etc)

January 19, 2018, 12:24 am
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If any document regarding voltage sources and it usage (vdc, vpulse..etc) , please send me a link.actually i not found any thing in google ..

Thanks,

Abhinav

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Long symbol label expressions disrupting Zoom to Fit

January 19, 2018, 1:52 pm
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I have some symbols that I've made in a Virtuoso schematic (version 6.17.709) that have some ILLabels labels containing code which evaluates to just a few characters to be displayed beside the symbol. Here's one of the labels:

if(cdfParseFloatString(ilInst->simM)==1 then sprintf(nil "%g/%g" 1e6*cdfParseFloatString(ilInst->w) 1e6*cdfParseFloatString(ilInst->l)) else sprintf(nil "%g@%g/%g" cdfParseFloatString(ilInst->simM) 1e6*cdfParseFloatString(ilInst->w) 1e6*cdfParseFloatString(ilInst->l)))

When I do a Zoom to Fit command for a schematic containing the instance, the resultant view yields an enormous amount of blank area because Virtuoso is assuming the full textual length of the label code is part of the stuff that needs to be catered for as viewable. The actual schematic ends up being tiny and I always have to do a manual zoom-in to see everything afterwards.

I guess the opposite situation could also occur i.e. the actual label text might be quite small but it evaluates to something really big that would subsequently be badly cropped with a Zoom to Fit. Zooming based on *evaluated* labels would keep everybody happy, but just ignoring labels altogether for figuring out a zoom would also be OK with me (because people very often put their schematic within a border frame).

Is there a way to configure Virtuoso to not yield all this gratuitous blank space? Many thanks in advance.

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Missing data.dm

January 21, 2018, 3:03 pm
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I'm trying to fix a symbol for a cell in Virtuoso and it won't let me save the symbol because the cell doesn't have a data.dm.  This cell has been  through a number of iterations and  it appears there has never been a  data.dm.  Is there any method to create one or fix the missing file?

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bath tub curve in cadence

January 22, 2018, 1:48 am
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Hi all,

I want to determine BER of high speed communication link. the expected BER is 1e-13. I read that typically bath tub curve is used for such problems, can you explain me how do I obtain bath tub curve in cadencd.

Thank you,

Kamlesh

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Calculator value() returns multiple values for given set of multiple x values as returned by cross()

January 23, 2018, 6:43 am
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Reference Thread = https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/23397/calculator-skill-function-for-sampling-signal-on-varying-pulse-edge

Is there a way for the value() or alternative function to accept an array of times that is returned by the cross() function similar to the one below, and return the values corresponding to those times ?

eg.

cross( VT("/vtest")) VAR("vdd33")/2 1 "rising"  t "time"  nil )

and then :

value( VT("/vout") cross( VT("/vtest")) VAR("vdd33")/2 1 "rising"  t "time"  nil ))

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Is there a way to describe the charge across the device as a function of voltage?

January 23, 2018, 10:25 pm
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Suppose I were to write the current across an ideal capacitor having terminals t1 and t2 and capacitance c. The code might look something like this:

   I(t1,t2) <+ c*ddt(V(t1,t2));

I'm trying to come up with a code that will instead keep track of the charge across the device like this:

Q(t1, t2) <+ .... ;

Where Q would keep track of the charge across the terminals.

Thank you for any feedback.
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Warning envSetval: Can't set the value of variable 'pathPurposeList', in tool......

January 24, 2018, 6:17 am
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Hi,

I am getting a series of warnings upon initialisation of Virtuoso. All errors are in the CIW window. All of the same type as below:

""Warning envSetval: Can't set the value of variable 'pathPurposeList', in tool......""

I have tried using "virtuoso -nocdsinit &" and all warnings go away but this generates a series of other warnings when new schematics are created or opened. I have looked in the cdsinit and cdsenv files but nothing I can see (in my limited experience) as obviously wrong.

Wondered if anyone could spot something wrong.

All files and CIW output attached.

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ERROR (USIMUWI-20008)

January 24, 2018, 12:34 pm
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Hello,

I am simulating a DC/DC Converter feedback loop. I have this error, that appears amid transient simulation in ADE:

Internal error found in spectre at time = 1.36483 ms during transient analysis `tran'.  
Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the Spectre log file, the behavioral model files, and any other information that can help identify the problem.
    FATAL: Internal error with exception. Terminating simulation.
Error found by spectre at time = 1.36483 ms during transient analysis `tran'.
    ERROR (USIMUWI-20008): The simulator failed to flush the stream for the format 'psfxl'. Check the format and supporting functions (for user defined formats) before running the simulation again.no error
Internal error found in spectre at time = 1.36483 ms during transient analysis `tran'.  
Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the Spectre log file, the behavioral model files, and any other information that can help identify the problem.
    FATAL (SPECTRE-21): Assertion failed.

Is it related to a setup or licensing issue? ( I simulated this loop before without error using the same setup )

Thanks.

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ADE-XL: Save statistical scatter plot setup

January 25, 2018, 8:23 am
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I've been making use of creating scatter plots of pairs of outputs in a Monte Carlo sim.  This has been very useful.  What is not so convenient is I haven't found a way to save my scatter plot setup to where I can automatically get my desired scatter plots after a simulation finishes.  I have to bring up the scatter plot form and pick my X and Y results each time.  Is there some way that I'm missing for storing this setup?

IC617 (6.1.7-64b.500.14), ADE-XL.

Thanks

-Dan

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