I am using Cadence Virtuoso on RHEL 5.9 and I am trying to run a simple program but the image enclosed says some error. I have been trying to diagnose it for a while now but haven't got any success yet. I wish somebody helped me with this on what to do cope up with this problem. I am a new user of Cadence.
Hi to everybody,
I am using Cadence IC.6.1, and was trying to understand the difference in terms of utility between design variables and parameters (iPar, pPar). I already know that we set the design variables in ADEL, and they are global, so for example if I put the length of all transistors in every subcell in a schematic equal to L, all will have this value. The function iPar() is used to make a CDF depedent on another CDF on the same instance, while pPar() can be used for one cell, and eventually the CDF parameters set with pPar() will appear near the symbol that I instantiate in my top-level schematic.
Now, I was trying to understand the advantages of these functions compared to each other: let's suppose we have two cascaded inverters, each corresponding to a symbol that I have in my top level schematic. Both have all transistors with W/L=2, and the second inverter has all transistors with a double size than the first one. Now, this can be done:
- with one design variable L, then directly setting in the properties of each transistors the width as a product of L and the respective numbers
- with one design variable L, setting the width of each transistor equal to iPar("l") multiplied by the respective numbers
- with one design variable L, setting the width of each transistor equal to pPar() in the properties of the cellviews
If I want to perform a parametric analysis sweeping L, I don't see any advantage in using iPar() and pPar(), neither if I also want to eventually sweep W. Could you maybe better explain in which situation (or an example) it is advantageous to use them? Thank you,
Nicola
hello
i am using virtuoso ic6.1.5. i want to find conversion gain of my circuit which have different input and output frequencies. which analysis should i use in cadence? why s parameter analysis donot works.
good day
arwah
Hi,
All of you might use probes in schematic viewing. Along the way, you add more and more probes (by doing 9 and select nets). At some point you might want to remove all probes and start over by I would like to know a way to make a hot key to remove all the probes (highlights) in a schematic by Create-> Probe--> Remove All. It is pretty painful to go through this again and again.
Could anyone provide a short cut key to do this?
Thanks.
ELiang
Hi,
I'd like to do the hierarchy copy to a self-contained library. How should I do? I'm okay to use SKILL or GUI operation. Thanks!
The design has different libraries across the hierarchy which can be described as below:
- schematic, layout can be from different libraries
- layout, symbol view name can be something different from default and has no known naming rules (e.g. symbol_left, symbol_right, layout_left, layout_right ...)
I'm not sure whether "Hierarchy copy" + "Exact hierarchy" + "Extra views" in Library manager can do this but the problem is I don't know all the non-default view names of layout or symbol (e.g. layout_left, symbol_small ...)
schematic hierarchy example:
LibA / cellA / schematic
-> LibA / cellAAA / symbol_left
-> LibB / cellBBB / symbol_right
-> LibC / cellCCC / symbol
layout hierarchy example:
LibA / cellA / layout
-> LibA / cellAAA / layout_left
-> LibB / cellBBB / layout_right
-> LibC / cellCCC / layout
Hi All,
There is a default display file from foundry and don't want to modify directly. But would like to use a different display file to load some personal settings. Can we define a short cut key to switch between two display files?
Thanks.
ELiang
Hi Cadence Forum
I am working on a chip layout and I want to place the pins of the current hierarchy layout so that it will be over the pins of a sub block.
Please see image below for clarity.
Thank you in advance.
Best regards,
I would like to generate variable pulse width based on the circuit conditions. I can use vpulse/vsource from analoglib to generate pulse with different duty cycles. But I am wondering, how to change or customize vpulse to change the pulse width during the simulation (dynamically based on the circuit condition)
Thanks in advance
Regards,
Vijay
Hi, is there a way to turn off the pulldown selection in ICADV12.3, which appears in several places (library manager, and also in create new instance form), .e.g in the attached image, for create instance of an analogLib res symbol, if I hit the Enter key, the lib field changes to the next lib in my library list, which is not desired, instead of the desired behavior = "Hide" the form which was the default behavior in previous versions. Thanks.
Hi Everyone
I want to introduce self-defined connectRules for AMS simulation to remove 1nsec sampling time from the predefined connectRules of the project
I have following the tutorial from Candence, and successfully create connectRules.il file for modified connection rules library.
Within the AMS setup form, I can also select this modified rules, but when running the simulation I got the error message for missing connect module.
Beside, when I try to view the connection module in the setup form, I also got the error message as shown below:
It seems that my connect rules are not introduced successfully, can someone help me to figure it out, which part is wrong.
P.S the original connect rules work fine, and the verilogams file to define the connect rules are the same, except assigning a new rule name after the modification.
I am using Virtuoso 6.1.6.500.14
Best Regards
Yi
ADE offers the inclusion of DSPF-files with the option that the internal nodes are interpreted case-sensitively.
When doing the same with ocean via ocnDspfFile(...) , no option is offered to activated the same behavior.. How is it supposed to be set up ?
On the technology I am using the default via width for the top metal is not DRC clean for our application.
I figured I could make a via variant to solve this.
The issue is that once a variant is made, its rows and columns are fixed e.g. if I make a variant and leave the rows and columns at 1x1, every array I make using the variant will be fixed at a size of 1x1.
This was asked two years ago but there was no real solution given.
Any ideas?
We are using Assura 4.15. When running DRC, the errors are listed in the ELW. When we try to locate the errors in the layout, error markers are visible (barely) because it does not "Zoom to Error". It doesn't matter what Zoom Ratio we enter in the ELW Preferences. Is there some other setting that is preventing the zooming ?
We can "Zoom to Error" only if we view the Error Report and select the 'Shape'. Is this a necessary step ? Is there a way to make the errors more visible directly from the ELW ?
thanks,
jill (cadence noob)
I want to design a voltage doubler(Using Dickson charge pump with 2 clocks) with
input voltage=Vdd=3.3V
output voltage=approximately =>6 volts
Frequency=1MHz
capacitance=5pF
I took period of clock as 2 us and width as 1 us.(zero value=3.3V and one calue=0 v)
I want the Mosfet's in saturation but they are either in region 0 or 3.Please help me out in working this circuit.
Hi ,
Scenario : I am using cadence version IC6177 , layout xl and exploring auto route option for routing between analog modules. On right clicking the net , choosing the option .. net ->route with wire assistant overrrides , the routing of that particular net is done. But the issues is , the routing is done over the modules and not in the free space though the module has blockage and dummy exclude layers.
Is there any way to avoid the routing over the modules?
I tried to set the environmental variable - setTreatBlockageAsMetalLayers with the following command
envSetVal("layoutXL" "setTreatBlockageAsMetalLayers" 'boolean t)
And error occurs , saying this value cant be set.
Please suggest some ways to execute.
Thanks,
Anand
hi
i am using virtuoso layout suite (v IC6.1.5.500.16.2). While using the vncap form technology library of 65nm CMOS; i am getting following error:
" adjacent (interdigitated) Mx or By fingers must be on different nets.
where x=1-6 and y=1,2,A,B "
actually this capacitor is being used as a matching capacitor between two differential nodes of balun output (custom made). Therefore both end of cap are referring to same net.
It can be solved by splitting cap and making differential but want to know about the solution in case when this splitting is not possible.
thanks
zubair
hello,
I have run 100 times tran sim by parametric sweep in adexl. In each run, I can use function "value" to find signal, Vx, at 5us. Then I can plot Vx by "plot all". Finally I can use function of "cross" to detect the crossing point position of Vx.
But I have no idea to write expression to find this crossing point directly. I don't want to manually plot curve for each corner. Can anybody give idea how to deal with parametric result efficiently ?
Best regards
I am trying to simulate a memristor model and check basic operations.
I got memristor source code written with verilog-a(below).
module memristor (p, n) ;
inout p, n ;
electrical p, n ;
parameter real uv = 10f;
parameter real d = 10n;
parameter real ron = 100;
parameter real roff = 38k;
parameter real rin = 5k;
real k, r1, r2, R;
analog begin
k = 2 * uv * ron * (roff - ron) / pow(d,2);
r1 = pow(rin,2) + k * idt( V(p,n), 0 );
r2 = min( pow(roff,2) , max(r1,pow(ron,2) ) );
R = sqrt(r2);
V(p,n) <+ R * I(p,n) ;
end
endmodule
And I created a cellview to add sin wave voltage source like below.
But when I simulated above module with ADE XL, Result is
Memristor has a constant resistance rin(of above code).
I think idt(...) of the code does not work. Should I do something more when simulate with verilog-a module?
Thank you.
I'm trying to use ADE-XL to sweep "length" for a resistor pcell. I clicked "Parameters" in the "Data View" pane and I select a parameter to sweep in the schematic
ADE-XL works correctly if:
ADE-XL results in "netl err" if:
*Error* eval: unbound variable - ATS_CB_VALUES
\o ERROR (ADE-6029): Netlisting failed because of errors in callback 'ats130resCB('l)' associated with param 'l'
\o of the lib 'temp' cell 'temp3' view 'schematic' inst 'R0'.
\o To complete netlisting, ensure that all the errors are corrected.
\o End netlisting Jan 10 00:32:26 2018
\o ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
\o ...unsuccessful.
\e *Error* Error during netlisting of design for the point ID (16 1).
\e ("error" 3 t nil ("*Error* "))
\e
\e
\o
\o *Error* Error ID = 5012
\o *Error* Error Msg = Failed to create netlist.
Is there a way to get around this?
Hello,
I am using an ST PDK ("ArtistKit") and I want to run a SIMPLE sim with local variations turned on. What I mean is that in a SINGLE RUN in ADE L, when I have two identical Common Source stages, the outputs should be different. I want to handle/plot the data entirely in ADE L.
Now I configured every single parameter that has to do with "Monte Carlo", "statistical" but if I run from ADE L the outputs of the 2 CS stages are just always identical, meaning that randomness to the transistors is applied and hence local variations do not work.
Instead now if I open ADE XL, load the ADE state from there and import the corners (as outlined in the documentation) it WORKS! But ONLY if I choose Run -> Monte Carlo Sampling (and as a workaround enter 1 Run). It does NOT work if I choose Run -> Single Run.
Looking in the output log I see:
Warning from spectre during Monte Carlo analysis `mc1'.
WARNING (SPECTRE-16006): mc1: Redundant monte carlo analysis was encountered. Neither scalar data nor waveform data will be saved.
This means that spectre must be aware that it is called in "mote carlo" mode and triggers the randomness of the models.
I do not like ADE XL, it is bloated, hard to understand and I just don't get why things don't work (for example, it does not save my output traces).
All I want is to have a single run with statistics enabled in ADE L (or, for that matter, a batch run started through ./runSimulation).
How can this be accomplished?
Thanks!