Hi,
When I try to run Monte Carlo it gives me a 3 items message for possible failure:
1. It says the machine selected in the current job setup policy isnot reachable
2. The Cadence hierarchy is not detected, not installed properly. or
3. Job start script (with a path and a name like swiftNetlistService#) is not found on the remote machines.
Any recommendation on how to fix this?
I decided it was time to update my spectre install (currently a version of Spectre211). Since 241 was a larger number than 211 I thought it would be a good idea (LOL)
Anyway, the simulator failed to run, and since I didn't have the time to debug why, I reverted to 211.
What's the difference in the two?
I need to add a new CDF parameter called "mag" to symbols in a given library using skill script in which the symbol size can be controlled and call back it each time this library is used so that all the symbols are updated.
IC 23.1-64b.ISR8.40
Hi all, I'm trying to run an stb analysis in a dspf extracted view via Probe terminal. The instance exist in the dspf and I already prepended the X that is placed in the dspf extraction. 
Spectre complains with the following error:
Error found by spectre during STB analysis `stb'.
ERROR (SPECTRE-16408): The probe parameter must be specified to perform stability analysis.
Analysis `stb' was terminated prematurely due to an error.
What is missing here?
Hi all,
I have a question regarding how to sweep the config view without using a global variable. I’d like to set a different config view for each test, and I'm trying to avoid using corners or plan.
Any suggestions on how to achieve this?
Thanks in advance for your help!
Best,
MooH
How can I place stacked vias with the size exact same cut width without metals around?
As the red part only in the image below?
For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.
My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?
Dear community
We would like to have more minimalistic and customized sheet borders for our schematics. I used this guide to create a starting point. Essentially, I made a copy of the US_8ths library and modified the Title symbol to look something like that:
Problem 1
The variable ilInst~>libName points to the library of the sheet border symbols, not to the library of the schematic. How do I need to modify this field in order to see the library name of the schematic where the border is instantiated?
Problem 2
The function CCSgetCreator() was taken from here. This solution does not seem to work with our management toll (we use VersIC); the function always returns nil as value. What is the simplest way to display the name of the user that created the schematic? A custom field that could be filled manually would also do the job for us; it doesn't need to be something that automatically fetches data from a database system.
Thanks for any input.
I want to use PSpice model (download from TI) in Virtuoso , but it can not work. Please help me to check the error message, Thanks
Parse error before token ']' in expression '[[STEADY_STATE]*0.6]'. If '[[STEADY_STATE]*0.6]' is a spice expression, quotes are required for the expression.
I need to include Verilog-A files which live outside the Cadence ecosystem (i.e., they are not in veriloga views but rather are just text files) into a veriloga view. These external modules are not compatible with OA (parametized port widths) so I can't put them into cellviews and hook them together using schematics.
Example: I have a cellview "test" which has a symbol and veriloga view. I have three "externaI" modules mod1 (inside an external file mod1.va), mod2 (inside an external file mod2.va), and mod3 (inside an external file mod3.va). I instantiate one instance of each module in "module test". The three modules have some parametized ports which are interconnected by parameterized signals p1 and p2. These two signals are strictly local to the module.
At the bottom of the module I use "`include mod1.va", "`mod2.va", etc.
When I check and save test->veriloga it checks all the included modules as well as the "test" module. However, I get a warning:
Warning from spectre during AHDL compile.
WARNING (VACOMP-1047): The Verilog-A file contains more than one module
definition. ADE can process only one module per Verilog-A file. Put
only one module in each Verilog-A file so that ADE can identify pin
names, directions, and hierarchy within each separate module.
Is this just a SUGGESTION that I can safely ignore, or are my included modules going to be ignored?
Hello,
I would like to use the simulation software xrun/simvision that comes with XCELIUM. We are currently using classroom licenses and want to disable all ip addresses on the student pcs except the license server ip. We want to make sure that students cannot copy confidential data from the Cadence tools.
Problem:
When I launch the xrun simulation while all ip addresses are blocked, it starts but the performance is very slow. The GUI starts after 5 minutes and the simulation is ready after 10 minutes. The interesting thing is that when I enable all blocked ip addresses, everything works at a reasonable speed.
Terminal Output (execution without internet connection):
xrun -gui design.vhd
waiting for SimVision/Verisium Debug to connect...
Is there a way to run the simulation tools without an Internet connection? Or can you give me the ip addresses that are used by the simulation tools so that I can enable only those specific ips?
Regards,
Max
Hello Everybody
Recently, I want to design a high output Power Amplifier at 2.4GHz using TSMC 1P6M CMOS Bulk Process. I use its nmos_rf_25_6t transistor model to determine the approximate mosfet size
I use the most common Common-Source Differential Amplifier topology with neutralizing capacitor to improve its stability and power gain performance
Because I want to output large power, the size of mosfet is very large, the gate width is about 2mm, when I perform harmonic balance analysis, everything is alright, the OP1dB is about 28dBm (0.63Watt)
But When I perform Transient simulation, the magnitude of voltage and current waveform at the saturation point is too small, for voltgae, Vpeaking is about 50mV, for current, Ipeaking is about 5mA
I assume some reasons: the bsim4 model is not complete/ the virtuoso version is wrong (My virtuoso version is IC6.1.7-64b.500.21)/the spectre version is wrong (spectre version is 15.1.0 32bit)/the MMSIM version is wrong/Transient Simulation setting is wrong (the algorithm is select gear2only, but when I select other, like: trap, the results have no difference), the maxstep I set 5ps, minstep I set 2ps to improve simulation speed, I think this step is much smaller than the fundamental period (1/2.4e9≈416ps)
I have no idea how to solve this problem, please help me! Thank you very very much!
I have tried replicating the setup described in a previous post (here), with the proposed solution.
The MDL measurements return a value of 0 for all exported result but the first.
Using Viva I can actually see the correct value for each contribution.
I am using :
- Spectre 23.1.0.538.isr10
- Viva IC23.1-64b.ISR8.40
What should I do differently?
Thanks!
**** test.measure ****
Measurement Name : noi_testAnalysis Type : noisenoi_total = 6.9282e-06 r1_flicker = 0 r1_thermal = 0 r1_total = 0 r2_flicker = 0 r2_thermal = 0 r2_total = 0
Hello
i did a sp-Analysis and now i want to extract the maximum value of the s11 trace and the corresponding frequency.
I already tried ymax() in the calculator but i am suspecting it only works on transient Signals.
Hello,
I'm trying to characterize a full adder that use transmission gate.
Unfortunately, the power calculation are wrong for the cell are always negative.
Is there any method or commands that can can help in power calculation or add the power consumption by the input pins to the power calculation ?
Another question, Is liberate support the characterization or transmission gate cells as standard cells or I should use liberate AMS for these type of cells ?
Thanks in advance,
Tareq
Hello everyone,
I have a testbench for generating s2p files from a SP simulation that was working until few months ago. Today I have reopened (w/o making changes that I am aware of) and I get the error as shown below:
first I show the testbench settings:
notice how the s2p generation is disabled: the field "file" is left blank
in the corner I defined some parameters, "filename" is the word that is suppose to generate the name for the s2p. 
where the two variables are defined as follows
And now the output log:
spectre.out file gives the following error:
When clicking on the error message at "9", the input.scs file opens up and the line 9 gets highlighted in green
now, so far I understood that the problem seem to be related tom the "pathcds" variable, but I really don't understand what the error message here means, since I don't see any error in the input.scs file
by the way - if for instance I define the variable "filename" as shown below, then I get no errors:
thanks
Tommaso
Hi,
I'm searching for a way to get a quick overview of too low cpk-values after a montecarlo sim. The non-MC results have the spec and thus the easy/understandable red/green/(yellow) colorcoding, but for MC sims I don't get a highlight for high variations inside the limits.
Is this possible (besides copying each expression into avg()+3*std()) and ..-..)?
It would be really handy to scan through finished sims...
(My final application is then to export the table for my reports and documentation...)
Regards,
leo
Hi,
reading Verilog®-A Language Reference I found this description of ddt function I don't understand:
Use the time derivative operator to calculate the time derivative of an argument.
ddt( input [ , abstol | nature ] )
input is a dynamic expression.
abstol is a constant specifying the absolute tolerance that applies to the output of the ddt operator. Set abstol at the largest signal level that you consider negligible.
nature is a nature from which the absolute tolerance is to be derived.
Can anyone explain how abstol and nature are defined? how using them? an example would be really appreciated.
Thanks
Andrea
Hi
I have a rather strange question - is there a way to tell layout XL to NOT place the error/warning markers on a design when I open a cell? I do a lot of my layout by using arrays from placed instances and create mosaics that completely ignore the metadata that Layout XL uses with its bindings with schematic (and instances get deleted etc. but I do like using it to generate all my pins etc.) and it's just really annoying when I open a design that I know is LVS clean and since the connectivity metadata is all screwed up (because I did not use it to actually complete the layout) I have a design that's just blinking at me at every gate, source and drain. I typically delete them at the high level heirarchically but the second I go in and modify something and come back up it places all of them again. I know that if I flatten all the p cells it goes away but sometimes it's nice to have that piece of metadata but that's about it. Is there a way to "break" the features of XL like this? I realize what a weird question this is but it's becoming more of an issue since we moved to IC 23 from IC 6 where there is no longer a layout L that I can use free from these annoyances that can't use any of the connectivity metadata.
Thanks
Chris
Hello all,
I have run a simulation with a lot of instnaces extraction and the psf.trn is >= 200 Gb, I tried to load it with simvision and it just breaks.
I would like to ask if there is a way to open this file, e.g. if I could read only some time window e.g. from 10us -> 15us.
getVersion(t)
"sub-version ICADVM20.1-64b.500.34 "
XCELIUMMAIN23.03.001
thank you in advance