Hi all,

I'm trying to browse a .raw directory generated by spectremdl and view the waveforms inside in Viva XL, which always went smoothly in the past with IC617 and MMSIM151. However recently I started working at another institution that uses Virtuoso.6.18.000 and SPECTRE23.10.242, things seem different.

In particular, I set a loop for transient analysis sweeping a design parameter in .mdl file, then it performs multiple transient runs and save their results in the .raw directory, with no errors. Normally a group of transient waves of a selected signal would be displayed in the Viva window, but now only 1 waveform appears, which corresponds to the first parameter value. But when I checked the .raw dir, I saw there were multiple tran simulation results indexed as -000.tran.tran, -001.tran.tran, -002.tran.tran, etc, and if I delete -000 files, the -001 can then be displayed in Viva, but -002. and later waveforms still cant be loaded.

I have also tried to run loop simulations using ADE L, the PSF results under the simulation/ directory can be displayed correctly. TBH I don't quite understand the differences between the .raw and psf result format. 

Does anyone have any ideas on this? Thank you in advance for your time and help!

Huang

Hi, 
These errors occurred while running Quantus(Assura).

Cadence Quantus Extraction - 64-bit Parasitic Extractor - Version
20.1.1-s233 Wed Mar 25 13:13:47 PDT 2020
---------------------------------------------------------------------------------------------------------------
Copyright 2020 Cadence Design Systems,
Inc.

INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
INFO (LBRCXU-108): Starting

/cadence/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/sameer23185/thesis/2020_1/SCH_lay/__qrc.rcx_cmd -t -f /home/sameer23185/thesis/2020_1/SCH_lay/extview.tmp -w /home/sameer23185/thesis/2020_1/SCH_lay
WARNING (LBRCXU-172): m2write fd 10, 1 tries, bytes -1 of 38, errno 9 Bad file descriptor

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.46s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.8-64b:IC6.1.8-64b.83 12/20/2018 04:06 (sjfib187) $
sub-version 4.1_USR6, integ signature 2018-12-20-0335

run on edatools-server1.iiitd.edu.in from /cadence/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Mon Oct 14 21:05:59 2024

Loading tech rule set file : /cadence/FOUNDRY/analog/180nm/pv/assura/techRuleSets
*WARNING* LIB functional from File /home/sameer23185/thesis/2020_1/cds.lib Line 4 redefines
LIB functional from File /cadence/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib
Insert UNDEFINE functional
before DEFINE functional
in /home/sameer23185/thesis/2020_1/cds.lib
Or remove or comment out DEFINE functional
in /cadence/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib
to suppress this warning message.
*WARNING* LIB US_8ths from File /home/sameer23185/thesis/2020_1/cds.lib Line 6 redefines
LIB US_8ths from File /cadence/FOUNDRY/cds.lib
Insert UNDEFINE US_8ths
before DEFINE US_8ths
in /home/sameer23185/thesis/2020_1/cds.lib
Or remove or comment out DEFINE US_8ths
in /cadence/FOUNDRY/cds.lib
to suppress this warning message.
*WARNING* The directory: '/cadence/ASSURA41/tools.lnx86/dfII/etc/cdslib/artist/functional' does not exist
but was defined in libFile '/home/sameer23185/thesis/2020_1/cds.lib' for Lib 'functional'.
*WARNING* The directory: '/cadence/ASSURA41/tools.lnx86/dfII/etc/cdslib/artist/analogLib' does not exist
but was defined in libFile '/home/sameer23185/thesis/2020_1/cds.lib' for Lib 'analogLib'.
*WARNING* LIB functional from File /home/sameer23185/thesis/2020_1/cds.lib Line 4 redefines
LIB functional from File /cadence/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib
Insert UNDEFINE functional
before DEFINE functional
in /home/sameer23185/thesis/2020_1/cds.lib
Or remove or comment out DEFINE functional
in /cadence/IC618/tools.lnx86/dfII/etc/cdsDotLibs/artist/cds.lib
to suppress this warning message.
*WARNING* LIB US_8ths from File /home/sameer23185/thesis/2020_1/cds.lib Line 6 redefines
LIB US_8ths from File /cadence/FOUNDRY/cds.lib
Insert UNDEFINE US_8ths
before DEFINE US_8ths
in /home/sameer23185/thesis/2020_1/cds.lib
Or remove or comment out DEFINE US_8ths
in /cadence/FOUNDRY/cds.lib
to suppress this warning message.
*WARNING* The directory: '/cadence/ASSURA41/tools.lnx86/dfII/etc/cdslib/artist/functional' does not exist
but was defined in libFile '/home/sameer23185/thesis/2020_1/cds.lib' for Lib 'functional'.
*WARNING* The directory: '/cadence/ASSURA41/tools.lnx86/dfII/etc/cdslib/artist/analogLib' does not exist
but was defined in libFile '/home/sameer23185/thesis/2020_1/cds.lib' for Lib 'analogLib'.
Loading gpdk180/libInit.il ...
Loading gpdk180/loadCxt.ile ... done!
Loading context 'gpdk180' from library 'gpdk180' ... done!
Loading context 'pdkUtils' from library 'gpdk180' ... done!
Loading gpdk180/.cdsenv ... *WARNING* Cannot find /cadence/ASSURA41/tools.lnx86/dfII/etc/tools/spectre directory to load environment variables
done!
Loading gpdk180/libInitCustomExit.il ...
*************************************************************
* Cadence Design Systems, Inc. *
* *
* Generic 180nm PDK *
* (gpdk180) *
* *
* Version 3.2 *
* *
*************************************************************
done!
Loaded gpdk180/libInit.il successfully!
*WARNING* Cannot find /cadence/ASSURA41/tools.lnx86/dfII/etc/tools/hspiceD directory to load environment variables
Loading gpdk045/libInit.il ...
Loading context 'gpdk045' from library 'gpdk045' ... done!
Loading gpdk045/gpdk045_customFilter.il ... done!
Loading gpdk045/libInitCustomExit.il ...
Loading Environment Settings ...
Loading gpdk045/gpdk045_PDKRegistrations.il ... done!

*************************************************************
* Cadence Design Systems, Inc. *
* *
* Generic 45nm PDK *
* (gpdk045) *
* *
*************************************************************

VERSION: 6.0 (09-September-2019)

done!
Loaded gpdk045/libInit.il successfully!
Loading gpdk090/libInit.il ...
Loading context 'gpdk090' from library 'gpdk090' ... done!
Loading gpdk090/gpdk090_customFilter.il ... done!
Loading gpdk090/.simrc ... done!
Loading gpdk090/libInitCustomExit.il ... Loading Environment Settings ...
*WARNING* envSetVal: Can't set the value of variable 'extractVerifySubstrate',
in tool[.partition] 'layout' - it has not been registered.
*WARNING* Cannot find /cadence/ASSURA41/tools.lnx86/dfII/etc/tools/spectre directory to load environment variables
*WARNING* envSetVal: could not find tool[.partition] 'spectre.envOpts'
*WARNING* Cannot find /cadence/ASSURA41/tools.lnx86/dfII/etc/tools/hspiceD directory to load environment variables
Loading gpdk090/gpdk090_PDKRegistrations.il ... done!

*************************************************************
* Cadence Design Systems, Inc. *
* *
* Generic 90nm PDK *
* (gpdk090) *
* *
*************************************************************

Version : 4.6

Build date: 10-FEB-2011

done!
Loaded gpdk090/libInit.il successfully!
*WARNING* envSetVal: could not find tool[.partition] 'hspiceD.envOpts'
ERROR: Failed to find a cellview for (presistor)

ERROR: Assura is terminating because some library models do not exist.
Your rules and your dfII model libraries are inconsistent.
Assura requires all library models in the rule file be present
in the database when running rcx with the "extracted_view"
option.

INFO (LBRCXU-111): Warning /cadence/ASSURA41/tools.lnx86/assura/bin/rcxToDfII exit with bad status

INFO (LBRCXU-112): Warning Status 256

INFO (LBRCXU-113): Warning Quantus execution terminated

***** aveng fork terminated abnormally *****

Hello,

we imported a layout from an older technology which has a min. BEOL grid of 0.005µm to a new technology which has a min. grid of 0.01µm. Is there an efficient way to move all offgrid shapes on the new grid?
Since the layout is quite large, it would save us a lot of work if there was an automated solution.

Best Regards

Hello all,

I have a question regarding the simulation of mixed-signal or clocked analog circuits in Spectre, particularly when the clock is not provided for the entire transient simulation.

My specific concern is if the clock is gated using a simple AND gate (or a behavioral AND gate), does Spectre automatically isolate the clocked (high-frequency) nodes from the rest of the circuit?
Does Spectre inherently optimize time steps such that when the clock is not enabled, only the clock nets are evaluated in small time steps while the rest of the circuit can be evaluated in much longer time steps?

If Spectre doesn't handle this optimization inherently, are there ways to improve simulation efficiency?
For instance, could using a Verilog-A based clock generator help optimize the time steps?

Any insights or experiences you can share would be greatly appreciated.

Thanks in advance,

Michael

Hi there,

I am facing a problem when using the layout function to do further design. The other components like mosfets could work well. But the mimcap was shown with a red box filled with a red 'x'. I would like to know what could be the source of this problem and how I could solve this. The graph about the problem is attched to this post.

I am trying to measure ISI jitter using delay function between PRBS pattern output (includes DCD+ISI jitter) & Clk pattern output (includes DCD jitter only). I need delay seperately for rise & fall edges. For Rise2Rise delay, function should capture only delay between rising edges of both signals at the same time, not at different times. Same is applicable to fall delay also. This delay, either Rise2Rise or Fall2Fall, will eliminate common DCD jitter and left with ISI jitter only. But my delay expression is not working properly. Below image (shared in link) clearly shows what I am trying to measure. Please help.

ISI Jitter Measurement Plots

* Unable to attach image due to unknown error. So, I am sharing image link. Error - An error occurred. Please try again or contact your administrator.

Hi

To simplify the placement of digital standard cells, I'd like to define a bind key that sets the following grid controls:

• Type = Lines
• Minor Spacing = 1.4 um
• Major Spacing = 5.6 um
• X Snap Spacing = 0.7 um
• Y Snap Spacing = 0.7 um

Based on the documentation and various forum threads I came up with the following SKILL code that's placed in the .cdsinit:

procedure(ChangeLayoutSnaps()
    hiGetCurrentWindow()->xSnapSpacing=700
    hiGetCurrentWindow()->ySnapSpacing=700
    hiGetCurrentWindow()->GridSpacing=1.4
    hiGetCurrentWindow()->GridMultiple=4
    hiGetCurrentWindow()->drawDottedGridOn=0
) ;proc

hiSetBindKey("Layout" "<Key>2" "ChangeLayoutSnaps")

This code properly sets the X and Y snap spacing, but does not affect the other three setting (grid type and minor/major spacing).

Could you point me to the issue in my code? Thanks very much for your help.

PS: This technology seems to have nm, not um, as default units, that's why the snap spacing is entered in nm. I've tried to also use nm for the minor/grid spacing, with no change in behavior.

Hello,

I am using VirtuosoStudio IC23.1.

I am running simulations in Virtuoso Assembler, and by default, the Detail view opens automatically when a simulation successfully completes. However, I would prefer the Checks/Asserts view to open by default after the simulation finishes, instead of having to manually switch to it each time.

Is there a way to configure Virtuoso Assembler so that the Checks/Asserts view is automatically displayed upon simulation completion? This configuration should apply for all users and be effective each time Cadence is launched.

I would appreciate any guidance on how to set this up.

Thank you!

Can

Hello,

I am using IC23.1.

Normally, I can manually enable design checks and asserts to be printed in the simulation log by going to Options→ Analog...→ Check, and then selecting "both" for the checklimitfile option. However, if this is not done manually, the design checks and asserts do not appear in the simulation log.

I would like to configure Virtuoso Assembler so that design checks and asserts are always printed in the simulation log file automatically, without needing manual intervention. This setting should apply for all users and be effective whenever Cadence is launched.

Could you please guide me on how to make this the default behavior?

Thank you!

Can

Hi, 

I'm trying to assign a bind key to space key, it's working fine in one workspace setup with Virtuoso Studio IC23.1 , but it's not working in a different workspace on another technology setup with Virtuoso ICADVM20.1. I think virtuoso is not reading the Space key from keyboard. Does anyone know if there is an environment variable that I need to set/reset in order for the Space key to work properly.

Thanks,

Prasad

I am using the psf_utils python package by Ken Kundert (https://pypi.org/project/psf-utils/) to do some signal post processing in python. I chose the format as psf and not psfxl in save options form but python still throws the following error while reading the tran.tran.tran file:

how do i ensure the psf tran.tran.tran file is being stored as ascii rather than binary format??

Hi, all. I use bash-script + ocean to batch run AMS while find it's not flexible and efficiency, is the "runams" the best solution? My need includues:

1) batch run many stimulus/cases
2) netlists includes verilog verilogams veriloga systemverilog, VHDL and spectre
3) better possible to be compatible with UVM later

Is any advice, Manuals or RAK recommended? thank you!

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

1. Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?

2. Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

Virtuoso IC Studio IC23.1-64b.ISR8.40

I'm having issues probing signals from an extracted view and the guides in the support.cadence.com are wrong as well.From the results browser I probe the voltage of interest and get this expression:

v("u_lfxo.u_gp_lfxo_top\\/u_agc\\/in_cmp_p" ?result "tran")

So one would think that using u_lfxo.u_gp_lfxo_top\\/u_agc\\/in_cmp_p as signal path in the deep probe does the job. However, nothing gets probed.

I found this in the forum:

deepprobe not working for extracted cellview in ADE-XL run.

But the suggested underscore would also be a problem because we use underscores in the instance names. What other character could be used as delimiter that does not require escaping in the deep probe syntax? Honestly this is a task that should be very straightforward to but the tool behavior is buggy.

Hi,

I have a question about printing noise summary via maestro output expressions.

How can I print noise data using output expressions, for multiple levels of the hierarchy?

I have found this article which describe the procedure using ocnGenNoiseSummary() function: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000007MViHEAW&pageName=ArticleContent

I see also Andrew Beckett referring to the above mentioned article as a solution to a similar question: community.cadence.com/.../noise-summary-per-instance

However, this seems to work only if I'm to extract noise data from a single level of hierarchy.

If I have the output expression "ocnGenNoiseSummary(2 ?result 'hbnoise)", it will generate a "noisesummary" directory under results directory for a hierarchy level of 2.

If I am to extract data from various hierarchy levels, I should be able to generate multiple noise summary directories, such as noisesummary1, noisesummary2 where they correspond to "ocnGenNoiseSummary(1 ?result 'hbnoise)" & "ocnGenNoiseSummary(2 ?result 'hbnoise)", respectively. However this does not seem to be possible.

Can you please advice? Thanks.

My Cadence version: IC23.1-64b.ISR7.27

BR,

Denizhan Karaca

Hi everyone,

I'm currently working on my thesis, which involves a beamformer system using CMOS 65nm technology. I'm trying to use the EMX tool for EM simulation but have encountered a few problems. Before diving into my questions about EMX, let me briefly explain how I conduct EM simulations with other software (ADS).

In ADS, I use the EM simulator with the Momentum microwave engine. However, my EM layout is quite large, and the mesh generated is extremely detailed, making it difficult to simulate the entire system. As a workaround, I divide the system into smaller parts and simulate each one individually. I've attached a snapshot of my setup, which includes an amplifier and a 1-to-2 Wilkinson power divider. I've separated these circuits and placed pins to facilitate EM simulations for each. I also placed ground pins at the boundaries of each circuit to connect them to the ground plane.

Here’s the link to the image (I'm unable to upload it due to an error): https://drive.google.com/file/d/13Qn4-DvMBj_K1JQLXrTWaWZ8uaLJr15u/view?usp=sharing

Now, moving on to EMX (version 6.3). For a maximum frequency of 31 GHz, I set the edge mesh = thickness = 0.4 µm (approximately the skin depth). However, when I simulate the circuit (amplifier + divider), the mesh on the ground plane becomes very dense, which makes running the simulation impossible due to excessive memory requirements. I reverted to my ADS approach and divided the circuit into two parts, placing ports to connect them. Unfortunately, EMX doesn't allow me to place multiple edge ports on the same edge for the ground plane, which has left me confused. Here are a couple of questions I have:

1. Is breaking the circuit into smaller parts a valid approach? Given the large ground plane, the mesh size for the ground is significant, making simulations challenging. Are there any methods to manage this issue?

2. Regarding the ground pins, why can't I place multiple edge ports to connect the ground planes of both circuits as I did in ADS? If this approach is incorrect, could you suggest alternative methods for simulating individual circuits and connecting them to estimate system performance?

Any insights would be greatly appreciated. Thank you in advance for your help!

Hi

In the environment I'm currently working, axes are shown for schematic, symbol, and layout views.For schematics and symbols, I'd prefer a dim gray, such that the axes are just visible but not dominant. For the layout, I'd prefer a brighter color. Is there a way to realize this? So far when I change the color of the 'axis' layer in the display resource editor, the axes in all three views get changed together:

Thanks very much for your input!

Dear all,

I defined two design variables in ADE Assembler, say V1 and V2, that define the voltage 1 and voltage 2 of a "vpulse" voltage source in my schematic.

Then, I define V1 = 1.0, and V2 = 2.0, run a transient simulation, and everything is as expexcted. The source provides pulses between 1.0 V and 2.0 V.

Next, I set V1 = 1.0:0.5:1.5, thereby creating a parametric sweep with 1.0 V and 1.5 V for V1. I keep V2 at 2.0 V. Then the simulation fails, and all I get is "netl err" in my Output Expressions and an error message that the results directory does not exist and nothing can be plotted: This is reasonable, as the results directory is deleted on starting a new simulation, and as there is no simulation result, none of my output expressions can be plotted.

WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
        Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
WARNING (ADE-1065): No simulation results are available.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.

Normally, this kind of para,metric sweep is not a problem, I have done this many times before. There must be something special in THIS PARTICULAR test bench or simulator setup. The trouble is, I don't get any useful error messages.

Does anyone know what might be the problem here OR where to find useful information to investigate further (log files stored somewhere)? Thank you!

Regards,

Volker

P.S. Using Corners instead does not help either. Running it through all values by hand works, though.

I need to characterize a cell that has capacitance and resistance , I specified leafcell, but something went wrong, here is the ERROR:

ERROR (SFE-396): "/home/IC/Project/smic18ee_lab/K_library/lab/MODELS/smic18ee_standalone/e2r018_real5v_v0p2_3t_spe.mdl" 839: Model `rnpo2sabe2r' has already been defined.

ERROR (SFE-396): "/home/IC/Project/smic18ee_lab/K_library/lab/MODELS/smic18ee_standalone/e2r018_real5v_v0p2_3t_spe.mdl" 846: Model `pipe2r' has already been defined.

here is the input file :

# Liberate Characterization Tcl File
# MODS by Tom Briggs (C) 2018

# Set the run directory. Here we use PWD, but in a distributed
# environment, it is recommended to directly specify the full path
# instead of using "PWD"
set rundir $env(PWD)

# Create the directories Liberate will write to.
exec mkdir -p ${rundir}/LDB
exec mkdir -p ${rundir}/LIBRARY
exec mkdir -p ${rundir}/DATASHEET

set_operating_condition -voltage 5 -temp 25
set_var extsim_model_include ${rundir}/MODELS/smic18ee_standalone/include_ff.scs

# d g s b
define_leafcell -type nmos -pin_position { 0 1 2 3 } \
{ nlv50e2r }

define_leafcell -type pmos -pin_position { 0 1 2 3 } \
{ plv50e2r }
## ----------------------------------------
define_leafcell -extsim_model -type c -pin_position { 0 1 } \
{ pipe2r }
define_leafcell -extsim_model -type r -pin_position { 0 1 } \
{ rnpo2sabe2r }

source ${rundir}/TEMPLATE/template.tcl

## Load Spice models and subckts ##
#set spicefiles $rundir/MODELS/include_SS.sp
foreach cell $cells {
lappend spicefiles ${rundir}/NETLIST/${cell}.scs
}

read_spice -format spectre ${spicefiles}

#read_spice -format spectre ${rundir}/NETLIST/INVX1.scs

## Characterize the library for NLDM (default), CCS and ECSM timing.
##char_library -ccs -ecsm -cells {dff_x1}
char_library -cells ${cells}
## Save characterization database for post-processing ##
write_ldb ${rundir}/LDB/ship_cells.ldb
write_library -overwrite ${rundir}/LIBRARY/ship_ccs_adder.lib
write_datasheet -format html -dir ${rundir}/DATASHEET "Ship Libs"

Hi,

I have a LEF file with simple definitions of pad design which uses M8, M9, and AP layers. However, I failed to import the design with CIW > Import > LEF... as I encountered "ERROR: (OALEFDEF-90019): Ignoring the line 30 in the layer map file ... as it contains a syntax error. Each entry in the layer map file must have two values, LEFLayerName and OALayerNumber separated by a blank space." All lines in the file report the same OALEFDEF-90019 error.

The tech.layermap file looks like this:


# techLayer       techPurpose     stream# dataType

ref drawing 0 0
DNW drawing 1 0
PW drawing 2 0