Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

I did not find any particular error in the log files and I'm running it on a RHEL 8 with sufficient memory. Please let me know how I could attach the file for the debug.

Celsius Version: 24.0.1.07031.519846

I created a new Verilog cellview in the library I usually use in Virtuoso, and wrote the following code:

module digitalinverter (Vin,Vout);
    input wire Vin;
    output wire Vout;

    assign Vout=~Vin;

endmodule

However, when I go to click the "Build a database of instances, nets, and pins found in file," I get the following popup, as well as the pasted CIW output.

CIW Output:

(TE-4223): Extracting cellview 'FA24SP25Analog digitalinverter functional' ...
Loading hdlPkg.cxt
ERROR (TIVLOG-43): The module 'digitalinverter' is not found in the source file inside the cellview 'FA24SP25Analog digitalinverter functional'.
Correct the module name in the source file or rename the cell to resolve the error.
ERROR (TIVLOG-34): Unable to parse the file, '/home/dgk64/SKY130_PDK/FA24SP25Analog/digitalinverter/functional/verilog.v', for cellview '(FA24SP25Analog digitalinverter functional)'.

ERROR (TI-7001): Cannot load the connectivity information for cellview 'FA24SP25Analog/digitalinverter/functional' in text file
'/home/dgk64/SKY130_PDK/FA24SP25Analog/digitalinverter/functional/verilog.v'.
Verilog *E,PARSEERR: Either there are parsing errors or cell digitalinverter
                    is not found in /home/dgk64/SKY130_PDK/FA24SP25Analog/digitalinverter/functional/verilog.v
                    file.
*WARNING* (TE-4309): Extract failed for cellview 'FA24SP25Analog digitalinverter functional'

The below is also what I have in my source file that I run before launching Virtuoso, in case that is relevant here:

#Cadence Virtuoso
module load cadence/cadence
module load cadence/innovus
#For parasitic extraction:
export ASSURAHOME=/opt/cadence/assura
export PATH=$ASSURAHOME/tools/bin:$PATH
export QRC_HOME=/opt/cadence/EXT152
export PATH=$QRC_HOME/bin:$QRC_HOME/tools/bin:$PATH
export PATH=/opt/cadence/SPECTRE231/bin:$PATH
unset OA_HOME
#
export CDS_Netlisting_Mode=Analog
# SKY130 Specific Pegasus
export OA_HOME=~/SKY130_PDK/oa
export PEGASUS_DRC=~/SKY130_PDK/sky130_release/Sky130_DRC
export PEGASUS_LVS=~/SKY130_PDK/sky130_release/Sky130_LVS
~                                                               

Thank you in advance!

Hello!

I know that Assura can be run from the command line using "assura rsfName". Is it possible to similarly launch the run results viewer that opens when clicking the "Open Run" button?

Hello,

I am using IC23.1 and running AMS simulations on ADE Assembler.

I am encountering an issue while running a large number of corner/MC mismatch simulations (1000+ runs). To speed up the simulations, I set the Max. Jobs parameter to a value greater than 1 under Options > Job Policy > Simulation/Netlisting. However, when this value is increased, some simulation runs fail, and I receive the following error in the xrun.log:

FATAL (SPECTRE-209): Cannot run the simulation because the required license could not be checked out. Check the license usage in the license server or use the license queuing feature (+lqtimeout <timeout_value> in the command line) to wait until the required license is available. For more information about +lqtimeout, type 'spectre -h'.
Notice from spectre.

I assume the failures are caused by all available license tokens being occupied when multiple simulation jobs are launched simultaneously. This results in subsequent runs being unable to acquire the required licenses, leading to the error.

My questions are:

1. Is my assumption correct, or could there be other factors causing these failures?
2. What can I do to prevent this issue from happening?
3. Is there a setting in the ADE Assembler GUI that would allow the tool to wait until a license becomes available instead of immediately killing the job and returning an error?

Thank you for your time and assistance.

Kind regards,

Can

Hi, all.  I have a design with multiple power supplys (1.8V 3.6V 5.5V) and multiple types of cellview (functional, verilogams, spice), RTL-1p8 means they are digital RTL codes (functional) and its outputs are suppled to be 1.8V as Logic-High. And what makes situation more complicated is that some of analog block are modeled as verilogams with both logic and electrical in/out

What I tried: If I config Vsuuply by instance, I cannot config both of them displine=logic; If I set the new line of IE-CARD displine as empty, it doesnt work as I wish.
My question is how to config IE-Card for this kind of design, Thank you.

Hello,

I am using IC23.1.

I am encountering an issue while running cascaded tests in ADE Assembler, specifically when using the calcVal function to transfer parameters between simulations. Below are the details of my setup and the problem:

Simulation Details

1. First Test (tran_calibration)

   • This performs a calibration under nominal conditions with fixed supply and temperature:
     • vdd = 1.8
     • temperature = 25
   • Outputs a calibration parameter (trim_calibrated), which is used in subsequent simulations.

2. Second Test (tran_slow)

   • This uses the calibrated value from tran_calibration:
     trim = calcVal("trim_calibrated" "tran_calibration" ?getFirstSweepPoint t)
   • The supply and temperature are swept to extreme corners:
     • vdd = 1.62, 1.98
     • temperature = -40, 85
   • The rise/fall time (t_rf) is set to a high value:
     • t_rf = 10

3. Third Test (tran_fast)

   • • This is similar to tran_slow but with a different rise/fall time:
       • t_rf = 1u
     • The supply and temperature are swept to extreme corners, same as the second test:
       • vdd = 1.62, 1.98
       • temperature = -40, 85
     • The calibrated value from tran_calibration:
       trim = calcVal("trim_calibrated" "tran_calibration" ?getFirstSweepPoint t)
     • The goal is to calculate an output (my_output) from tran_slow and inject it into tran_fast for each supply and temperature combination:
       • (vdd = 1.62, temperature = -40)
       • (vdd = 1.98, temperature = -40)
       • (vdd = 1.62, temperature = 85)
       • (vdd = 1.98, temperature = 85)

Issue

When attempting to use calcVal to transfer my_output from tran_slow to tran_fast, I encounter a netlisting error. I have tried the following expressions, but they all fail:

1. calcVal("my_output" "tran_slow" ?matchParams "all")
2. calcVal("my_output" "tran_slow" ?matchParams "all" ?ignoreParams list("t_rf"))
3. calcVal("my_output" "tran_slow" ?ignoreParams list("t_rf"))

I suspect the issue may be related to parameter matching, as t_rf differs between tran_slow and tran_fast.

Goal

My ultimate goal is to run exhaustive corner and Monte Carlo mismatch simulations as follows:

To clarify my goal for exhaustive corner simulations, here is an example of the process corner combinations I want to explore:

• device1: ss, sf, tt, fs, ff
• device2: ss, sf, tt, fs, ff
• device3: min, typ, max
• device4: min, typ, max

These values are just an example to illustrate my intention and may not represent the actual parameters in my design.

• Corners: 225 process corners × 9 simulations (1 tran_calibration, 4 tran_slow, 4 tran_fast) = 2025 runs.
• Monte Carlo: 100 iterations × 9 simulations = 900 runs.

Before scaling up, I need to ensure the cascaded simulation flow works correctly at nominal corners.

Additional Context

• I am running an AMS simulation.
• I am using the functional view for the mixed-signal blocks.

Request for Assistance

Could you guide me on the correct use of calcVal in this context, particularly for handling multiple parameter sweeps? Are there additional settings or best practices to ensure parameter consistency across cascaded simulations?

Thank you for your time and assistance. I look forward to your guidance to resolve this issue.

Best regards,

Can

IC23.1 ISR10.29

Hi,

I'm running an aging analysis using TMI models from TSMC. Using alter statements is a convenient way to run gradual aging or change other parameters through the sim. It works in command line spectre, but I'd like to be able to achieve this within the ADE explorer context, so I can access all my expressions and plot saves and see the impact of aging on my specs.

Using parameters in ADE explorer doesnt work as it starts a completely new sim without regard to the previous condition. Even if I manually edit the netlist to contain the alter statement and press (only) RUN (not netlist and run), the netlist gets recreated and I lose my alter statements.

Is there a way to achieve this in the ADE explorer context?

Regards

Dear all,

I wish to calculate the random jitter and deterministic jitter for a data transmission circuit.

Could anyone kindly guide me regarding which analysis I must run and what are the further steps after that?

Regards,

Tuka

Hello,

I am performing simulations of amplifiers and generating a datasheet to organize the amplifiers we have designed. For this, I am running simulations with ADE and exporting the data to MATLAB for processing. I need to send these results back to ADE to generate the datasheet. I am able to send a single data point, but I need to export multiple data points, organized with one for each corner.

In MATLAB, I have a vector whose components are the data for each corner, but when I call the MATLAB function in ADE, the result is returned as matlab:double.

Does anyone know how to assign each value of the result vector from my function to the corners so that they appear ordered under each column for each corner in the ADE results?

Thanks in advance!

Dear Community

Suppose I want to design a 5:1 current mirror. There are four ways to set up the circuit/simulation:

a) Make the width of one transistor 5 times bigger.
b) Make 5 instances of an unit-sized transistor to create one big device
c) Use the device multiplier (m-factor) with nullmfactorcorrelation=no
d) Use the device multiplier (m-factor) with nullmfactorcorrelation=yes

I would expect that:
- (b) and (d) are identical because in both situations we have 5 separate, uncorrelated devices.
- (a) and (c) are identical because 5 fully correlated, unit-sized devices should behave the same as one big device.
- (b) and (d) yield a higher variance than (a) and (c) because we assume the five unit-sized devices to be five statistically independent mismatch sources.

Here is what 1000 MC samples (mismatch only, fully random sampling) look like in Spectre:

The plot shows the standard deviation of the output current (in absolute numbers) versus the device area.
Quick side node: Doing version (a) in the simulator gives a small systematic error since the widths are unequal.

Question 1:
In contrast to my expectation, (a) is identical to (b) and (d). This makes sense in reality; it's a question of the absolute device area after all, if I use one big device or many smaller devices should not matter. But shouldn't the variance be higher when I tell the simulator to explicitly assume that the five instances are uncorrelated? What is happening under the hood here?

Question 2:
Version (c) looks a bit off. If you make the same simulation with another mirroring ratio, e.g. 1:1 or 20:1 (same output current, i.e. the bias current is scaled accordingly), the standard deviation of version (c) is always the same. In fact, every design point is exactly the same. That does not seem right to me. An explanation of the simulator's behaviour would be appreciated here.

Hi,

I designed a layout of a BGR with IC23.1 and used Calibre PEX to extract the parasitics of the design as a dspf file. I include the dspf file in simulation under the Setup > Simulation Files > Parasitic Files (DSPF) section. As I need to debug the BGR layout, I want to do out-of-context probing to probe the nets within it; however, despite modifying the ./.simrc in the simulation directory to include the dspf options as below, the netlist names still don't match and doesn't seem to be different to the netlist names before adding the dspf options. I am wondering if there is a way for me to check if the .simrc file is run or somewhere that I can specify the .simrc location. Additionally, if my setup of the dspfFileEnvOptions is correct.

dspfFileEnvOptions = '(
(nil
spfFileNameMappingFormat "cdl"
spfFileHierDelimiter "/"
spfFileTermDelimiter ":"
spfFileNetMapping "mixed"
spfFileDevicePrefixForTermCurrent "M"
spfFileAddPrefixToDevice "t"
spfFileTerminalMapping "lower"
)
)

In schematic I use keyboard shortcut 9 to highlight nets/ports(with wires) etc. But in a schematic I am not able to highlight a pin of another symbol which doesn't have a wire coming out. Is there a way to highlight it. Example below. Though both AVDD_1V_REG_DIG and DATA_OUT are no connects. I am able to highlight the DATA_OUT since it has a wire. While the highlight doesnt work on AVDD_1V_REG_DIG since there is no wire and it is directly the pin of the symbol view.

Also I observed that when I highlight a pin(that doesn't have a wire) then I need to zoom in and highlight a corner of the pin. Anywhere on the pin doesn't work. This is not a big issue. But if it can be fixed then it will be useful. Also highlighting the name of the pin doesn't work. Though when I hover over the name it hovers over the arc.

But when there is a wire connecting to the pin. Anywhere on the pin works. Only if there is no wire I need to zoom in and click on a corner. Highlighting name of the pin doesn't work even when there is a wire.

hi ,

i am doing AMS simulation with xcelium and spectre. It seems i only get a folder amscf.raw with timeSweep.tran.fsdb inside.

Can i specify an output name like Analog.fsdb instead of timeSweep.tran.fsdb.

Thanks

In below snapshot what is difference between beff and betaeff..?

one of them is combination of 1/2(µnCox)W/L and another is combination of µnCox but which one..? 

or it is something else.

Thank you.

I am running a 300 point monte carlo run where each corner takes quite long to simulate, I would like to break the single run into two separate runs of 150 jobs each, run them on separate machines and later combine the excel files for statistical processing. 
However how do i ensure that the 300 corners generated in the two separate runs are the same as those in a single run? Because if i use the same initial seed, i am going to get identical runs, if i use different seeds, i am still not sure how different the distribution is going to be.

What's the way to accomplish this?
Thanks

Hi,

I am using frequently the function swapSweep() function inside of Maestro and I would like to know if it is possible to use it inside an Ocean script.

If possible, can you send a simple example?

Thanks,

              Zeev

I'm using xrun 23.03-s009, virtuoso 23.1, ISR10.29.

For a top level simulation, our digital place and route is called out as external HDL in the hierarchy editor.  In the systemVerilog, it calls out an instance of an OTP cell.  Is it possible to have that OTP cell netlist using the schematic view?  The design will netlist, but fails because the OTP instance "is a leaf instance and is unresolved in cellview."

I've tried putting the library in the HED Library List, adding a netlist to the model path, and put an unconnected an instance of the OTP at the top level test bench so it would be netlisted.  Nothing has worked so far.  Any ideas?

Hi,

I used to extract the small signal parameters of transistors from dc sweep by defining in a file: save * sigtype=all. This worked and I had access to transistors' small signal parameters like gm, gds, etc.
Now, for certain advanced technology nodes of a certain fab transistors for analog design are defined as analog_cell, sort of a subcircuit. Or another possible definition is as macro model. These definitions capture more layout effects and non-idealities but doesn't give access to gm etc as before.
I was wondering if anyone knows and can help me understand how to extract the small signal transistor parameters in this case since the old approach doesn't quite work for those definitions.

Thanks

Hi I save a simulation results in ADE assembler as shown in the figure above.

and in the save directory a folder is generated which name is the library name, and I want to ask how do I load this data in maestro(ADE Exploer or ADE assembler). Thanks a lot