Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all 4899 articles
Browse latest View live
↧

Adapt .cal file to .rul file for PVS

April 22, 2024, 3:13 am
$
0
0

Hello there,

So I have been working with a specific PDK for Cadence designing and simulating analog circuits with Virtuoso and ADE. When doing the physical layout however, the files provided for the verification rules are intended to be used with the Siemens Calibre software (which I don't have access to), they have a .cal extension and the syntax is different than the .rul files that I have seen for other PDK's.

Is there a way to automatically transform this kind of files? Should it be done manually?

Thank you!

↧
Search

How to inquire the discipline of a specific net in an AMS simulation via systemVerilog

April 23, 2024, 3:35 am
$
0
0

I am using $cgav in a systemVerilog test to get a voltage from and electrical node in an AMS simulation.

The AMS simulation in based on a HED config that could have a specific block either as a schematic or a model, where a specific net could be either electrical or wreal/logic, in which case $cgav will not do what is required.

Is there a way to read or inquire the discipline of a specific net,  to then be able to use either $cgav or just to read the value of a discrete net ?

 

↧
↧

VSR: How to avoid router to route over floating fill

April 23, 2024, 6:24 am
$
0
0

Hi,

I am trying to resolve an issue where router is routing a metal layer directly on top of a floating fill layer of the same layer. Are there any constraints to set to avoid this. This is causing a short and thus failing LVS.

example:

m2 fill layer exists in the layout and not from the router. After VSR run finishes, ports are being connect and in the process the m2 drawing from the router draws directly on top of the m2 fill. How do we prevent this?

thanks!

↧

Fetching the operating point of a transistor in VerilogA with "$simprobe" always returns 0

April 23, 2024, 7:00 am
$
0
0

I have the following schematic:

"VerilogA_Test" block is written so that it takes the transconductance gm of the transistor MN0 and prints its value.

The VerilogA code is the following:

`include "constants.vams"
`include "disciplines.vams"

module VerilogA_Test;

    string path = "MN0";
    real val5;
    integer count;
    analog begin
            @ (initial_step) begin
            count=0;
        end
        if( count < 5 ) begin
            val5 = $simprobe(path,"gm");
            $display("\n Value of gm in Analog context is: %f\n",val5);
        end
        count = count+1;
     end
endmodule

Whether I run a DC or a transient simulation, the output of the $display function is always:

"Value of gm in Analog context is: 0.000000".

I followed the procedure described in: $simprobe support

What am I doing wrong? I am on Spectre version 21.1.0.389.isr8

Thank you in advance!

↧

Plotting Template in ADE Assembler and ADE Explorer

April 23, 2024, 1:54 pm
$
0
0

My virtuoso verison is: sub-version  IC6.1.8-64b.500.27 

I created two ADE Explorer cases and for each of them I saved a Plotting Template named differently such that no Plotting Template naming confusion exists between the two Explorer case, e.g. tb_bjt and tb_bjt_temp. Each explorer case run by itself refreshed the graphic results correctly. Then I tried to run both cases inside the  ADE Assembler. I could not find a way to get the two plotting windows as defined individually in the ADE Explorer. Can you help? Thank you, 

↧
↧

Snap grid setup

April 24, 2024, 3:56 am
$
0
0

Hi All,

I would like to setup grids, Right I don't see any snap pattern option on grids palette. 

This is how I want 

I am using cadence 6.1.8 version. please let me know how do I setup these grids.  

Thank you in advance

Best regards

Manjunath

↧

Allegro Constraint Manager - Array

April 24, 2024, 4:27 am
$
0
0

Hello,

I have a reference design from TI. When I looked at PCB's constraint manager for Spacing, I found there are array of values separated by colon in each section. What is the meaning of these values? I mean which value is taken?

Thanks

Santosh

↧

Transient Noise Analysis (fmin)

April 25, 2024, 1:47 am
$
0
0

Hello,

I try to set the fmin via Tran Noise Options to 1Hz. However, fmin is limited to 1/simulationTime no matter what I set. First of all, if I run AC noise analysis, I know that within the frequency band < 250Hz (which is 1/simulationTime), there is noise that adds up to the final value. I also would like to match the Tran noise result to AC noise result. For this reason I aim to simulate the noise in frequencies < 250Hz which is not possible for TRAN simulations unless I set the simulation time as 1s instead of 4ms.

I expect that if I run the simulation with multiple runs with simulation time equals 4ms, I should see the low frequency component independent of the simulation time (if fmin was indeed equal to the value I set as 1Hz). I expect that if I take the histogram of the signal (noise) at a certain time moment, the standard deviation should also correspond to the low frequencies. I believe I dont have to wait 1seconds to observe noise @ 1Hz. 

Can you please help me understand where I am making a mistake unless the tool is not suited to set fmin (even if you set) to a value < 1/simulationTime ?

Thank you in advance.

PS: I have seen this entry Transient Noise Simulation for Different input/output frequencies - Custom IC Design - Cadence Technology Forums - Cadence Community and response of Andrew below:

Andrew Beckett statement: That said, we now (in recent versions - IC617 together with SPECTRE161) set noisefmin to 1Hz by default rather than asking the user to enter it. This caused confusion and only saved a little simulation time with the improvements made in the analysis over recent years. So the noise you observe is going to be based on the duration of the simulation. 

The version I use is "@(#)$CDS: virtuoso version 6.1.8-64b 07/11/2023 19:24 (sjfhw317) $"

Best regards,

Emir

↧
Search

Skill Pcell "undefined function pow" at eval during LVS

April 25, 2024, 3:02 am
$
0
0

Hello,

I've been working on a PCell in skill for several days and it is not a piece of cake! I was able to fix most of my problems alone, but this time I really don't understand...

For a little of context I have a PCell that generates a layout and a schematic (therefore I have 2 pcDefinePCell).

When I generate the PCell (by loading the .il script) everything works fine. I see my layout and my schematic as expected.

When I implement the symbol of my pcell in a schematic, no problem, the layout is also generated as expected. DRC work perfectly.

But when I run the LVS, it won't work and I have this error:

Pcell evaluation for architectures_tests/pcell_inv/schematic generated information. See layer/purpose "marker/error" shape with property "drcWhy" for description. You can get more details from file /tmp/_pcEvala79387.

ERROR (OSSHNL-408): Failed to generate the netlist because of a Pcell evaluation error on cellview 'my_lib/pcell_inv/schematic'. Set simStopNetlistOnPcellFailure to "ignore" to prevent this error.

In the tmp file I have 2 times : *Error* eval: undefined function - pow

The thing is I don't have any "pow" function in my scripts... So I really don't understand.

I hope someone can help me. Thank you in advance!

↧
↧

Is spc file available in ADE Explorer/Assembler?

April 25, 2024, 5:02 am
$
0
0

Hello,

I am using an internal simulator as a shell around spectre and the input I have to give at least in older versions of Virtuoso was a .spc file. This was done by loading the ADE-L state, it would find this file. Is this file available now with the maestro view? By loading the maestro view our simulator does not recognize any .spc file.

KR,

Maria

↧

Refer to output expression by name, when name contains whitespaces and special characters

April 25, 2024, 5:41 am
$
0
0

Dear all,

IC6.1.4 and especially Virtuoso Studio 23.1 allows to name output expressions in ADE and then used those named output expressions in other expressions by simply using its name (reference by name).

Abritrary example:

Name: gain

Expression: VF("/net1")/VF("/net2")

Name: Output Amplitude

Expression: VF("/net3")*gain

Things get complicated when "Name" is a text containing whitespaces, like "Output Amplitude", and even worse, if special characters are involved (like "Gain at 20% bias current").

The first case still works in most cases, but in the latter case, the new output expression converts the name to "Gain at 0.2 bias current" (without quotes, of course), which is not the expression name any longer and hence fails.

Is there a way to safely refer to output expressions that are named by text containing whitespaces and/or special characters?

Simply putting the name between single or double quotes or parentheses does not work.

↧

Difference srrWave and drWave

April 25, 2024, 6:37 am
$
0
0

Going through the OCEAN Reference Manual the ocnPrint function mentions drWave as the waveform identifier. Checking the identifier of the results of my simulation, I get srrWave. What is the difference between the two?

↧

Load Pull simulations without PortAdapter

April 25, 2024, 9:12 am
$
0
0

Hi

I would like to run load pull simulations with harmonic balance analysis. I do not have access to PortAdapter from rfExamples library. So I would like to run it using analoglib port with hb analyses.  I need to set sweep for magnitude and theta of reflection coefficient and run the simulation. How should I set up the simulation? Especially, at the output port. Can you help, please?

Many thanks.

↧
↧

Auto placer not updating PR boundary

April 25, 2024, 2:45 pm
$
0
0

Hi All,

Could you take a look at the figure? I am trying to make the PR boundary on the left layout more compact and similar to the right. It seems the auto placer can do it, but sometimes it struggles. Is this a tool issue, or is some setting affecting this?

Regards

Supriyo

↧

LVS Mismatch

April 26, 2024, 1:11 am
$
0
0

Hello,

I added an LVS-cleaned design block at the top level with other blocks and components. At the top level, it is claiming again mismatched instances of the previously LVS cleaned block.

It's a 130nm SiGe BiCMOS process. Would you please give me some insights? Thanks

↧
Search

Virtuoso IC6.1.8-64b.500.31 Crashing

April 26, 2024, 2:33 pm
$
0
0


After running several heavy simulations through ADE Assembler, the Virtuoso tool occasionally crashes, displaying the "Fatal Application Error". The design is quite large, at about 3GB, so the netlisting might also be substantial. I have a script that performs various tasks such as submitting jobs, plotting results, netlisting, etc.

The memory report in the CIW indicates that I'm currently using 7,117MB out of 8,917MB. Here's the message:

"Memory report: using 7,117 MB, process size 8,917 MB at UTC 2024.04.23 21:01:12.502"

It appears that memory usage is increasing as I run more memory-intensive MMSIM jobs. However, when I log the current memory allocated using the memoryAllocated() function between my SKILL functions, there is little to no change in memory. This leads me to believe that my SKILL script is not contributing to the memory usage.

Please note that I'm running all my MMSIM jobs in an HPC environment with ample RAM and CPU resources and I am running my netlisting jobs locally. The version I'm using is IC6.1.8-64b.500.31, and the CDS_AUTO_64BIT environment variable is set to "ALL".

I'm unsure how to further troubleshoot this issue, so I'm open to any suggestions that may help. If necessary, I'll submit a support ticket.

↧

Maestro - design variables form fetching deleted variables

April 29, 2024, 1:22 am
$
0
0

I'm not sure how & why design variables is still fetching old variables which are deleted & replaced with values. Simulation will run fine but, when I click 'copy from cellview', old variables show up. This is happening even with new Maestro. Is there any form in schematic which has this data?

virtuoso version ICADVM20.1-64b.500.34

↧
↧

"Ignore Instances" not completely ignoring capacitor instance effects

April 29, 2024, 4:32 am
$
0
0

I'm simulating a CS-DAC, and was experimenting with the effect of an extra capacitor on the tail node. 

To do that, I placed an ideal cap from analogLib on the node, and then measured in three cases:

  • No capacitor installed,

  • 100fF capacitor installed,

  • 100fF capacitor installed but ignored

Here are the results:

As you can see, there's almost no difference between ignoring or not ignoring the cap! I assumed the ignore instance option would cause it to act like the case without any capacitor.

I would appreciate your suggestions.

Best regards,
Mahdi

↧

ocnPrint to File

April 29, 2024, 6:09 am
$
0
0

Using `ocnPrint` to write a waveform to a file, I am unable to locate the file it writes to if it even writes to the file. I have tried relative and absolute paths and searched through the simulation results directory, `getSkillPath()`directories, as well as the project location. Oddly enough the output that should be printed to the file is printed in the CIW. The OCEAN commands are called through Python-Skill Bridge, which simply allows to use OCEAN commands in Python for further processing.

How can I use the `ocnPrint`-function to write the waveform to a findable file?

# copied from File > Create Script... in maestro
ws['ocnSetXLMode']("explorer") # set mode to OCEANXL
ws['ocnxlProjectDir']("~/simulations") # location of simulation results
ws['ocnxlTargetCellView']("Library", "cell", "view") # substituted values by general names
ws['ocnxlResultsLocation']("") # same as project dir
ws['ocnxlSimResultsLocation']("") # same as project dir
ws['ocnxlMaxJobFail'](20)
# own addition
ws['openResults'](path_data)
ws['selectResult'](Symbol("tran"))
data=ws['getData']("/net1")
res=ws['ocnPrint']("?output", "./myOutputFile", data) # copied from OCEAN reference guide
↧

How to use device models with spectre circuit simulator

April 29, 2024, 7:08 am
$
0
0

Hi,

I'm trying to use HiSIM2 with ADE-L.

I read "Spectre Circuit Simulator Components and Device Models Reference". I believe the model is supported by cadence.

However, I got the error below when I ran ADE-L simulation.

Error found by spectre during hierarchy flattening.
ERROR (CMI-2119): I17: Cannot instantiate the hisim2 type instance using a primitive. Instantiate the instance using a model and rerun the simulation.

How do I use the models supported by cadence?

Below is my netlist

===========

// Generated for: spectre
// Generated on: Apr 29 10:06:50 2024
// Design library name: TCAS_IVR
// Design cell name: hvsim
// Design view name: schematic
simulator lang=spectre
global 0
parameters vds=1 vgs=1

// Library name: TCAS_IVR
// Cell name: hvsim
// View name: schematic
V7 (net1 0) vsource dc=vgs type=dc
V6 (net2 0) vsource dc=vds type=dc
I17 (net2 net1 0 0) hisim2 w=10u l=10u
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=1u errpreset=moderate write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save I17:d
saveOptions options save=allpub

↧
Viewing all 4899 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>