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Extract x and y Vector from srrWave

April 29, 2024, 7:37 am
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The goal is to extract the x and y vectors from an srrWave. In a first step from a single design point, but in a later stage ideally from a parameter sweep simulation. The current approach to get the x and y vectors from a waveform from a node voltage of a transient simulation is shown below. The code is written in Python. Python-Skill Bridge is used to forward the OCEAN commands. The function extracting the x and y vectors:

defwave2vec(ws, waveform):
x_vec= ws.dr.get_waveform_x_vec(waveform)
x= []
print(f'Vector length: {ws.dr.vector_length(x_vec)}')
foriinrange(ws.dr.vector_length(x_vec)):
x.append(ws.dr.get_elem(x_vec, i))
y_vec= ws.dr.get_waveform_y_vec(waveform)
y= []
print(f'Vector length: {ws.dr.vector_length(y_vec)}')
foriinrange(ws.dr.vector_length(y_vec)):
y.append(ws.dr.get_elem(y_vec, i))
returnx, y

Getting the waveform data from the simulation results and calling wave2vec:

# setup Maestro mode explorer
ws['ocnSetXLMode']("explorer") # set mode to OCEANXL
ws['ocnxlProjectDir']("~/simulations") # location of simulation results
ws['ocnxlTargetCellView']("library", "cell", "view")
ws['ocnxlResultsLocation']("") # same as project dir
ws['ocnxlSimResultsLocation']("") # same as project dir
ws['ocnxlMaxJobFail'](20)

ws['openResults'](path_data)
results=ws['results']()
ws['selectResult'](Symbol("tran"))
data=ws['getData']("/net1")
x, y=wave2vec(ws, data)

The data variable does hold the correct result, i.e. the node votlages in an srrWave object (from a similar post), and the code runs without errors. However, the return values from `wave2vec` are not as expected: x returns [1.0] and y returns [<remote object0x...>].

How can I change the method above to correctly access the x and y vectors of an srrWave in case of a single design point and, if possible, in case of a parameter sweep simulation?

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skill to get csh date time format instead of getCurrentTime from skill

April 30, 2024, 1:04 am
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i will like to record the time while executing my callback.

However, i can get "Apr 3016:00:35 2024" with getCurrentTime.

i prefer to have format like "20240430_160038" with "date +%Y%m%d_%H%M%S" of csh.

Don't know how to call csh and get the format.

second question. 

i have existing script written with perl.

how to execute that script and get the result from it by skill code?

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Virtuoso - align instances to match pin order

April 30, 2024, 4:17 am
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Hello,

I would like to align levelshifts to match pinout order from a hard IP block.

There are various levelshifter types being used so they need to be in the correct order.

In the past I have used the digital placer for this task reasonable successfully.

  1. Is there a function in IC studio to perform this task?
  2. Is there a function to select or deselect every Nth instance/via selected?
    1. Sometimes need to rotate or flip ever 2nd or 3rd selected device.
  3. Is there a function to drop contacts onto a MOS device gate automatically?
    1. Sometimes this is built into pcells or we have custom SKILL. I need to understand whether to continue supporting existing SKILL functions or IC23 can replace them.

Thanks in advance,

Paul.

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Flash ADC

April 30, 2024, 7:52 am
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Hello everyone,

I need to test a 3 bit  Flash ADC in ADE Explorer. For an analog input (such as a sinewave) it gives in output a digital bit stream. How can I process this signal/data? I have to obtain the typical staircase signal in order to measure INL/DNL.
how to get this staircase signal?

Thank you in advance.

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Trouble netlising using analogLib Mosfet symbol

May 2, 2024, 11:50 am
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I am trying to simulate a custom mosfet model utilising the analogLib Mosfet symbol. The circuit should form a simple inverter.

While the schematic looks good (see picture) the netlist does not and ADE says as much in the output log

Error found by spectre during hierarchy flattening.
    ERROR (CMI-2116): M2: Too few terminals given (0 < 3).
    ERROR (CMI-2116): M0: Too few terminals given (0 < 3).

I never have needed to do this before so I am unfamiliar with utilising the in built symbols but looking at the symbol it does have four appropriate terminals (see symbol properties picture)

Netlist produced for ADE:

// Generated for: spectre
// Generated on: May  2 19:02:26 2024
// Design library name: test
// Design cell name: INV
// Design view name: schematic
simulator lang=spectre
global 0
include "/home/Cadence/my_rundir/myPDK/models/hspice/my_TT.pm"

// Library name: test
// Cell name: INV
// View name: schematic
M2 pmos_lvt
M0 nmos_lvt
simulatorOptions options psfversion="1.4.0" reltol=1e-3 vabstol=1e-6 \
    iabstol=1e-12 temp=27 tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 \
    maxnotes=5 maxwarns=5 digits=5 cols=80 pivrel=1e-3 \
    sensfile="../psf/sens.output" checklimitdest=psf
tran tran stop=10n errpreset=conservative write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

I'll include only the first modified line of the model:

** My TT models

** Hspice modelcard
.model nmos_lvt nmos level = 72

I do not want to use hspice but I think spectre will read in an hspice file, in anycase the netlist is wrong therefore the schematic needs sorting first.

Obviously there may not be enough information but I'll add this as required not to make the post too long.

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Modifying the ADE Assembler "Open MATLAB" command

May 3, 2024, 3:45 pm
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Hello

Currently, when I click on "Open MATLAB" via the ADE Assembler, another matlab version is opened (an older version that doesn't support Mixed-Signal Analyzer).

I can fix this if I had a way to modify the command that Cadence executes to launch a newer matlab version (I just need to point to the correct MATLAB version that I have).

I suspect "Open MATLAB" simply executes "matlab" through a terminal... but I have a separate command that launches a more modern version 

thanks in advance

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How to setup ADE Explorer to save last N runs automatically

May 4, 2024, 10:14 pm
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How to setup ADE Explorer to save last N runs automatically? With ADE-L the following line in .cdsinit would save the last 5 runs. 

envSetVal("asimenv.misc" "numberOfSavedRuns" 'int 5)

Thanks

Nagendra

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How to save all device terminal voltage waveforms in spectre?

May 6, 2024, 6:23 am
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I have a large netlist and when I generate a list of specific device terminals such as below,  the waveforms are saved.

save top.foo.bar.foo_bar.my_ckt.nmos_a.g

save top.foo.bar.foo_bar.my_ckt.nmos_a.s

save top.foo.bar.foo_bar.my_ckt.nmos_a.d

But if I simply try 

save *.g

save *.s

save *.d

or even

save *g

save *s

save *d

The waveforms don't seem to be saved

I have used wildcards in the past but I don't think I have ever tried something this simple.  

I assume I am missing something very simple?

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Transient Simulation of a Capacitive Charge Pump Circuit

May 7, 2024, 2:58 am
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Dear forum members,

I am trying to simulate a simple circuit which is phase one of a two phased capacitive charge pump. It is a 3 capacitor, 2 in parallel and 1 in series with the others making a capacitive divider that can give a voltage ratio of 2/3rd of its supply voltage. I have inserted one nmos as a switch to keep things simple. The schematic is below:

I perform a transient simulation of this circuit but the voltage at Vcfly node never rises. The NMOS switch is kept very big to get a low Ron. The solutions I have tried for convergence is keeping cmin=1pF, skipdc=yes but so far no luck. The transient simulation is shown below/

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Help needed in resolving gpdk180 warning issue

May 8, 2024, 12:40 am
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*WARNING* ddMapGetFileViewType: You are trying to run an OA executable on a CDB library file 'symbol.cdb'. The file is in library 'gpdk180' in cell 'nmos' in view 'symbol'. Use cdb2oa to convert your data from CDB to OA and then try again.

I'm getting the following error while trying to use the gpdk180 library.

I'm a complete novice. Please assist in resolving the issue.

Also, while trying to "Attach an existing technology file" when creating a new library, the gpdk file does not show. Can someone tell what might be the case?

Software: Virtuoso 6.1.8

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Monte Carlo simulations not proceedings for the last few jobs/points

May 10, 2024, 6:56 am
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Hello All, 

I have been observing my MC simulation which starts of completely fine with multiple jobs running in parallel but towards the end when only a few jobs are left it seems to get stagnated and not moving forward for hours and the number of running jobs reduces to one. 

The schematic simulates completes fast and fine but not the extracted view which halts as indicated in the below  screenshot. Suspending and resuming the job doesn't help. 

In some posts I see suggestion to use LSCS. In my case I am using the LBS job setup mode in IC618 ISR31. I don't see any specific option to select LSCS Vs ICRP. 

Any suggestions/tips will be very helpful. 

thanks 

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ViVA- set different color to each psf

May 11, 2024, 4:07 pm
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Is there a way to set only one color to all waveforms under single psf? This will help when comparing 2 psf data, say different corners/testcases. Right now, I'm changing color manually by selecting required waveforms.

virtuoso version ICADVM20.1-64b.500.34

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create single wire context sensitive menu

May 12, 2024, 10:00 pm
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I do not get create single wire context sensitive menu, after right clicking on wire. could please tell me how to enable this option

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FATAL (SPECTRE-20): Illegal instruction: seems something wrong addressing S-parameter

May 14, 2024, 2:51 am
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Hi~

I just installed Spectre181 and have a problem that when I did something with my S-parameter, it showed the message like below.

It's weird because when I imported a less ports S-parameter like .s2p and it could run smoothly.

However, when I run with more ports S-parameter, it failed.

I typed command: spectre +spice +aps -64  <xxxx.sp>

does anyone has similar experience?

************************************************************************************************

Reading file: /home/rogerchen/Downloads/test/send/10361.S23P

Notice from spectre during hierarchy flattening.
Nport compression is disabled on instance spfile_pcb because its used port ratio 1.000000 is greater than 0.800000.

Time for EDB Visiting: CPU = 0.296875 s, elapsed = 0.302316 s.
Time accumulated: CPU = 0.453125 s, elapsed = 4.09891 s.
Peak resident memory used = 6.85e+07 bytes.


Internal error found in spectre during initial setup.
Encountered a critical error during simulation. Please run `mmsimpack' to pack the test case (use mmsimpack -h option to get detailed usage), and submit the case via Cadence Online Support, including the package tar file and any
other information that can help identify the problem.
FATAL (SPECTRE-20): Illegal instruction.

Version 18.1.0.077 64bit -- 1 Aug 2018

****ASSERTION STACK****
0x47ebfce
0x51bc0e
0x7fe271e7ef10
0x7fe2660e36b2
0x7fe2660fddb5
0x7fe2660f8e17
0x7fe27a4f08a8
0x7fe27a33a7d5
0x7fe27a370f36
0x7fe27ba67353
0x2fb3a0c
0x2f78099
0xe8bb5a
0xe95ffa
0xe75a3e
0xe75af1
0x531277
0x5ff9a7
0x604237
0x60440d
0x54f867
0x55b83f
0x55ceae
0x4a2189
0x7fe271e61c87
0x4f6025
/opt/cadence/SPECTRE181/tools/bin/spectre[80]: .: line 1164: 6398: Abort(coredump)
Aborted (core dumped)

************************************************************************************************

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How to override the default values using Verilog netlist.

May 14, 2024, 6:14 pm
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I am trying to import a netlist to generate an array of verilog-a module block (for test doublerr. va).  I have already created a cell and symbol for this module.  when importing the netlist the array is made but with the default parameter values. how to override the default values?

doublerr. va

`include "constants.vams"
`include "disciplines.vams"


module vdoublerr (in, out);
input in;
output out;
electrical in, out;
parameter real parm1 = 0.2;
parameter real parm2 = 0.1;
parameter real parm3 = 5.0;

analog begin
V(out) <+ (parm1 + parm2 + parm3) * V(in);
end

endmodule

Netlist

`timescale 1ns / 1ns
module netlisting_500_schematic (clause, data);

inout [1:2] clause;
inout [1:4] data;


specify
specparam CDS_LIBNAME = "netlisting";
specparam CDS_CELLNAME = "netlisting_500_schematic";
specparam CDS_VIEWNAME = "schematic";
endspecify

vdoublerr I3 (.out(clause[2]), .in(data[4]));
vdoublerr I2 (.out(clause[2]), .in(data[3]));
vdoublerr I1 (.out(clause[1]), .in(data[2]));
vdoublerr I0 (.out(clause[1]), .in(data[1]));
defparam
I0.parm1 = 100.0;

endmodule

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Export layout from Layout XL

May 15, 2024, 6:57 am
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Hi,

I would like to export a layout view from Layout Suite XL in order to manipulate it outside of Virtuoso.

I can achieve something with strmout which lets me create a .gds file, however it is a lossy procedure.

Is there any other way? If more information is needed please ask.

Thanks.

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Could anyone explain PSS+PAC simulation result of sampling circuit

May 15, 2024, 9:37 am
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Hi, the answer to my question is certainly trivial, I perform a PSS+PAC analysis to simulate the response of a sampling circuit made up of an ideal switch (RonSW=200 ohms) followed by a capacitance of CT=80pF.  When the switch is continuously on, I obtain a cutoff frequency at -3dB of 10MHz which corresponds to the expected value while when the switch is clocked at the frequency of 50MHz the cutoff frequencyis divided by two, i.e. 5MHz. I suspect that this is due to spectral aliasing but I do not understand the division by a factor of two of the bandwidth.Could anyone give me an explanation ?

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Virtuoso version update issue

May 16, 2024, 2:55 am
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Which sub version of 6.1.8 does the following function start from? When simulating STB, virtuoso will automatically add ". IPRB-DM" to the netlist.
For example, analysis ('stb? Start "1"? Stop "1000M"? Probe "I0. IPRB-DM"? UsingProbeMode t)
What I have learned is that IC6.1.8-64b.83 does not have this feature yet, while IC6.1.8-64b.500.30 already has this feature.

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Create schematic from netlist(verilog)

May 16, 2024, 7:27 am
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I am looking to create a schematic from a netlist(verilog) file. The verilog file just has connections of different modules. It doesnt have any logic(behaviouiral verilog code).

Example:
Say I have a cell sample_core which has a symbol view. Among other input and output ports it also has 4 outputs o_w,o_x,o_y,o_z each 7:0.
I want to create a sample_wrap cell which does some rewiring of sample_core. But I dont want to do it manually in schematic. So I will create a verilog file that does the rewiring and want to generate a schematic and symbol views from the verilog. Example given below.  This verilog file I will generate using some script to avoid mistakes.


module sample_wrap

(

//some many other inputs and outputs

output [3:0] o_a,

output [3:0] o_b,

output [3:0] o_c,

output [3:0] o_d,

output [3:0] o_e,

output [3:0] o_f,

output [3:0] o_g,

output [3:0] o_h

);

sample_core I_sample_core

(

//some many other inputs and outputs

.o_w({o_h[0],o_g[0],o_f[0],o_e[0],o_d[0],o_c[0],o_b[0],o_a[0]}),

.o_x({o_h[1],o_g[1],o_f[1],o_e[1],o_d[1],o_c[1],o_b[1],o_a[1]}),

.o_y({o_h[2],o_g[2],o_f[2],o_e[2],o_d[2],o_c[2],o_b[2],o_a[2]}),

.o_z({o_h[3],o_g[3],o_f[3],o_e[3],o_d[3],o_c[3],o_b[3],o_a[3]}),

);

endmodule

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Explorer to run an AMS simulation by copying the files rather than using their absolute path

May 17, 2024, 6:50 am
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I know it is possible from ADE Explorer to export simulation scripts for xrun, where we can choose the files to be set as absolute path or copy files.

But if we do a run on the Virtuoso ADE Explorer, similar scripts are created where we would have xrunArgs and textInput files for the external HDL files, etc.

Is it possible to ask Virtuoso ADE Explorer to run an AMS simulation by copying the files rather than using their absolute path, as it is possible with the export tool?

 

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