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Netlist error

April 12, 2024, 7:58 am
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Greetings,

I'm a phd student in the rf design field. Usually (in my master formation at least) I used to work with cadence already installed and everything working perfectly from the beginning. 

However in the lab I'm working in I had to work with the it engineer to install everything from scratch.

the technology that we're working with is a new one Bicmos 55nm from Stmicroelectronics.

Currently I'm trying to simulate a schematic circuit in maestro and I have a netlist error. This is frustrating as it seems that I can't resolve this issue.

Begin Incremental Netlisting Apr 12 16:55:04 2024
ERROR (OSSHNL-116): Cannot descend into any of the views defined in the view list 'spectre cmos_sch cmos.sch schematic veriloga' specified
for library 'cmos065_rf' and cell 'npnxhs' for the instance 'Q0' in cell 'PA_cmos/inv/schematic'. Add
one of these views or modify the view list so that it contains an existing
view.

This is the error that I'm getting

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Finding usage of a cell inside other cells

April 12, 2024, 4:17 pm
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Hello, 

I am trying to find if a particular cell (from a different library) has been used (instantiated) in any other cells inside another set of  big libraries. Is there an easier and less error prone method to figure this out ?

regards

Sid

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Maestro - output expression values with suffix notation instead of engineering

April 12, 2024, 8:22 pm
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Output expression values like clip signal from 4m to 5m will convert them to engineering notation. Is there a way to retain values with suffix only? This is easier for repeated expression edits. Thanks.
virtuoso version ICADVM20.1-64b.500.34

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Input in 32 bit full adder

April 15, 2024, 8:55 am
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I have designed a 32 bit adder,Now i have to give  vpulse as input in 64 input pins.Please help me regarding it.

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VSR not dropping vias to short all pins

April 15, 2024, 3:09 pm
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I have multiple horizontal m2 layers (one on top of the other that have the same terminal and net name). The only diffrence is the pin names are different. VSR only connects only one pin at the top level after the run finishes. The expectation is that m3 would be extened from top to bottom of each horizontal m2 layer and a v2 is placed on each horizontal layer. Instead VSR only drops one v2 and call it quits. Why will VSR not connect all the pins together here?

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Maestro - save right click menu order from results tab

April 16, 2024, 1:13 am
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Is there a way to save right click menu order from results tab after customizing it? This will avoid re-customizing menus in newer workspaces?
virtuoso version ICADVM20.1-64b.500.34

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probe internal bus voltages

April 16, 2024, 5:22 am
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Hi,

I would like to probe 4sets of 8bit buses internal to a block (internal ADC outputs) from test bench level. At the test bench level, i will then be applying these bus voltages/signals to a veriloga block for further processing. Now, i am probing one internal net at a time using  a deepprobe each  by setting

heirarchical node to ADC.DIG1\<0\> on the deepprobe

May I know if there is a way to probe the whole bus at once, rather than probing one net at a time. That could be something like setting
heirarchical node to ADC.DIG1\<8\:0\>

Thank you!!

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ViVA - eye diagram entries are not allowing variable names

April 16, 2024, 7:44 am
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Eye diagram entries start, stop, & interval are not allowing variable name like VAR("stoptime"). Am I missing something here? Or it's not possible at all?
virtuoso version ICADVM20.1-64b.500.34

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ADE Assembler, History name prefix list

April 16, 2024, 10:16 pm
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Hello,

It might be simple one, but I did not find a way to delete the History name prefix list, as shown below. It is a convenient feature in Assembler, but as I keep running new sims, all the old names are kept in the list. How can I delete them?

Thanks!

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How to generate LIB and LEF file.

April 16, 2024, 10:39 pm
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Dear Sir,

I would like to ask, We got a TSMC 65nm foundry file for IC fabrication but i cant see any LIB and LEF file in the folder.

So, please suggest me how to get LIB and LEF file or us how to generate LIB and LEF file .

Please share the flow related steps such as how and which files we Import for the genration of LIB and LEF file.

Thanks 

Shiv

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extracting specific point in a MeasureAcrossSweep

April 18, 2024, 1:01 am
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Hi,

I do have a testbench where:

- a scaler value is getting measured

- many corners and uses cases are being swept through corners

- on top of that I sweep temperature across several points, this sweep is made in a local (or global) variable and is then "outside" the corner sweep

Now I want to measure the temperature coefficient of my scaler.

That is easy to do with a measure across sweep, if I only sweep 2 temperature points (I measure ymax and ymin of the scaler)

But now I'd like to automate things a bit more, and measure temco from -40 / 125 AND also tempo from 0 / 85 in the same testbebch

Is there a way, instead of calling for min or max value of the measure across sweep, to call for a specific entry of this list ?

I mean if my temperature points are -40, 0, 85 and 125. Can I specifically call for the 1st entry, the 2nd one, and so one ? 

BR

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How to specify the Spectre path or version for Liberate 15.1?

April 18, 2024, 3:51 am
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Hi,

How to specify the Spectre path or version for Liberate 15.1? Are there any Tcl commands or args to achieve this?

Thank you!

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Setting a routing only master instance transparent

April 18, 2024, 4:06 am
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I have a routing only cell which is repeatedly used in multiple hierarchies. Is there anyway I can set the master instance transparent, which when instantiated in different levels take binding names present at instantiated level similar to a group copied.

Sync group works only at 1 hierarchy.

Thanks,

Jitendra S.

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One testbench for different analysis (S-parameters, ac, transient)

April 19, 2024, 7:36 am
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How can I run different analyses (S-parameters, AC, transient) in a single test bench?

I tried connecting the sp1switch in series with the port, AC analysis, and transient work, but the S parameters were not correctly calculated. 
I have tried making a variable to turn on and off the switch, but it does two simulations. Since I wanted to use the optimization, so I wanted the results to be calculated with the same parameters. Not changing parameters. 

Please let me know how it can be done. 
Thank you.

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How to merge top cell with dummy metal GDS

April 20, 2024, 7:34 am
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Hello everyone,

I've been working on the final verification of my top-level design. I'm planning to merge my top cell with the dummy metal and dummy OD/PO layers for the final DRC check. However, when I merge and perform the DRC, I'm not getting the expected errors. It seems like there might be an issue with how I'm merging the files. Could someone please guide the correct way to merge the files to ensure I get the correct DRC results?

Thank you.

Regards,

Moin

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Evaluated waveform discontinuity

April 20, 2024, 9:07 pm
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Hello, 

I am using "freq" function to get a waveform representing the frequency of a signal versus time but at some of the corners I see the evaluated output of "freq" function as discontinuous. Screenshot below for reference where the yellow and red waveforms start abruptly after 1us.

Is there something I can do in the simulation settings or elsewhere to remove this discontinuity so that the waveforms start as the "green" one ?

regards 

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How to write an equation to measure pk-to-pk jitter from eye diagrams

April 21, 2024, 4:28 am
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Hi,

I have requirement to write equation to measure pk-to-pk jitter from eye diagrams.

I have following one queries in in the forum some I am not able match the jitter from manual measurement vs measure as per the following solution

Please do let me know if am missing anything here 

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Transient Noise Simulation in Cadence Virtuoso

April 22, 2024, 12:29 am
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Hi 

I am using Cadence Virtuoso IC6.1.8-64b.83.

For a demodulator with 140GHz carrier and 40Gbps data rate, i set the transient noise with only the demodulator noise contribution ON. When i simulate it with Fmax = 700GHz, it gives higher amplitude of demodulated output signal (34mv) where as when simulated with FMax = 280GHz it gives low amplitude of the detected output signal (24 mv). I did not set Fmin so put it as default 1Hz. What is the appropriate setting in this case? Thank you

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Maestro - dark theme background

April 22, 2024, 2:10 am
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Is there a way to set Maestro background to dark? For data view, output setup, results & ciw.
virtuoso version ICADVM20.1-64b.500.34

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Maestro - custom window size for simulation log

April 22, 2024, 2:15 am
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Each time I had to resize the window to see end of log file for runtime & cpu load. Is there a way to set custom size?
virtuoso version ICADVM20.1-64b.500.34

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