Hi,
in our simulation, we need to capture clock frequency changes which is very slowly and if we finish the transient sim and apply "frequency" function, it will require large disk even w. limited saved nets.
one work around can be chop the simulation to smaller runs and piece them together but that is tedious.
I wonder if there is any Verilog-A example code that could check crossing point of defined threshold and export that time point continuously to a file?
thanks!
Kevin
Hello！I build a differential OTA and use vcvs to get a CMFB, as follows:
The gain of E0 and E1 is 0.5. The gain of E4 is 1.
In ADE XL, I run 100 points of montecarlo simulation.
Then, I find the gain of E4 is 0 at some points! For example:
In summary, 13 points has wrong gain(The gain of E4 is 0) while 87 points has right gain(The gain of E4 is 1). The gain of E0 and E1 is all right at 100 points.
The settings of E4 is as follows:
My virtuoso version is 6.1.7-64b. My spectre version is 15.1.0.284.isr1 64bit -- 12 Nov 2015.
Is there anyway to solve this problem? Thank you!
I need to use a spice sub-circuit from LTspice in the Virtuoso schematic editor.
I copied and pasted the .subckt attached to a Spice text editor file. However, it gives me the following errors:
Error: Instance `B1': Unexpected value `uplim' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `v(1)' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `v(3)' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `0.2' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `0.1' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `v(4)' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `-0.2' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `0.1' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `+1n*V' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `1' - this element does not accept any positional parameters.
Error: Instance `B1': Unexpected value `-1.4705e-10' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `uplim' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `v(2)' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `v(3)' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `0.21' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `0.1' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `v(4)' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `-0.21' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `0.1' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `+1n*V' - this element does not accept any positional parameters.
Error: Instance `B2': Unexpected value `2' - this element does not accept any positional parameters.
simulator lang=spice
.subckt LTC6082 1 2 3 4 5
X1 2 1 0 0 0 0 0 0 OTA g=0 in=.5f
B1 0 N004 I=10u*dnlim(uplim(V(1),V(3)+.2,.1), V(4)-.2, .1)+1n*V(1)-147.05p
B2 N004 0 I=10u*dnlim(uplim(V(2),V(3)+.21,.1), V(4)-.21, .1)+1n*V(2)
C10 N004 0 50f Rpar=100K noiseless
M1 5 N011 4 4 NI temp=27
C2 3 5 1p Rpar=100Meg noiseless
D5 N011 4 DLIMN
M2 5 N007 3 3 PI temp=27
D8 3 N007 DLIMP
C3 3 N007 10f Rser=1.5Meg noiseless
X3 N008 N009 4 4 4 4 N007 4 OTA g=200n ref=-37m linear vlow=-1e308 vhigh=1e308
C11 5 4 1p Rpar=100Meg noiseless
C12 N011 4 10f Rser=1Meg noiseless
X4 0 N004 0 0 0 0 N005 0 OTA g=1u linear en=12.6n enk=55.4 Vhigh=1e308 Vlow=-1e308
C16 N009 5 790f
X5 N006 0 N008 N008 N008 N008 N009 N008 OTA g=18u iout=1.4u Vhigh=1e308 Vlow=-1e308
G1 4 N011 N009 N008 200n
D9 N009 N008 DLIM
C7 3 1 3.5p Rser=10 Rpar=5T noiseless
C13 3 4 1000p
C1 N005 0 105f Rpar=1Meg noiseless
G2 0 N008 4 0 .5m
G4 0 N008 3 0 .5m
C18 N008 0 200p Rpar=1K noiseless
D1 2 1 DIN
G3 0 N006 N005 0 1m
L1 N006 0 170µ Cpar=177f Rser=1.07k Rpar=15.28k noiseless
C9 N007 5 50f Rser=1.5Meg noiseless
C8 5 N011 50f Rser=1.5Meg noiseless
C4 3 2 3.5p Rser=10 Rpar=5T noiseless
C5 1 4 3.5p Rser=10 Rpar=5T noiseless
C6 2 4 3.5p Rser=10 Rpar=5T noiseless
D3 3 2 DBIAS
D4 3 1 DBIAS
D6 2 3 DESD
D7 4 2 DESD
D10 1 3 DESD
D11 4 1 DESD
D2 3 4 DPOW
.model DIN D(Ron=1k Roff=10T Vfwd=1.5 epsilon=.1 Vrev=1.5 revepsilon=.1 noiseless)
.model DBIAS D(Ron=1g Roff=1T epsilon=.3 ilimit=.2p noiseless)
.model DPOW D(Ron=1k Roff=1G Vfwd=.1 epsilon=50m ilimit=252.8u noiseless)
.model NI VDMOS(Vto=300m kp=30m lambda=.01)
.model PI VDMOS(Vto=-300m Kp=30m lambda=.01 pchan)
.model DLIM D(Ron=100k Roff=70Meg Vfwd=200m Vrev=200m epsilon=10m revepsilon=10m noiseless)
.model DESD D(Ron=10 Roff=10T Vfwd=.7 epsilon=.1 noiseless)
.model DLIMN D(Ron=100k Roff=100Meg Vfwd=1.65 Vrev=-300m epsilon=.1 noiseless)
.model DLIMP D(Ron=100k Roff=100Meg Vfwd=1.55 Vrev=-300m epsilon=10m revepsilon=10m noiseless)
.ends LTC6082
*
Hi,
I am doing stb analysis of an opamp within my circuit.
During schematic simulation (spectre), the phase plot stats from 180 degree and then goes down to 0.
However, extracted netlist simulation, the phase plot stats from 0 degree and then goes up to 90 and falls back.
Is it a simulator issue?! Or does it mean at DC there is a positive feedback?!
Note: Transient response exhibits no positive feedback.
Kindly give your response!
I hope to load a skill script directly in Bash to modify the layout and generate GDS. Is there a way to accomplish this without starting Virtuoso? Alternatively, which scripts does Virtuoso load before invoking procedures like dbOpenCellView?
There are two independent loops in my circuit that I want to run stability analysis for. Since a Maestro Test can have only one analysis of a given type, I have two Tests. The only difference between the two tests is the terminal I specify for "Probe Terminal" in the stb analysis configuration. I am running over corners and the DC solution can take a while to converge.
Is it possible to use the DC solution from my Loop1 Test in my Loop2 test? Somehow I have to match the DC solution between the two Tests corner-to-corner. I don't know how to do that.
Assembler/Explorer from Virtuoso version IC6.1.8-64b.500.32
Hello everyone,
I made a copy of a cell that has schematic and layout views. Both original and new copied cells are in the same library. Then I started schematic editing on the copied cell. But whenever I opened the layout, it always referred to the original cell's schematic as physConfig. I tried deleting the physConfig view of the copied cell, but it created a new one of the original cell. How can I link the new schematic to the copied cell?
Thanks!
Hi all, I am running a long transient anaylsis, where I got the following error during the simulation:
ERROR (SPECTRE-16928): Cannot run the simulation because transient analysis has reached the maximum number of times allowed to approach minstep (within 5% of stop time or 5us, whichever is less). Use the 'max_approach_minstep' option to change the maximum number of times allowed to approach minstep and rerun the simulation.
Where can I find this 'max_approach_minstep' option? I searched in transient analysis option and 'Simulation' -> 'Options', but didn't see it. Or is there other ways to solve it?
I'm using ADE Explorer in IC618 with spectre 21.
By the way, does this error possibly result from a really tight simulation accuracy? I set 'reltol' to 1e-5 to reach the desired accuracy.
I am trying to run LVS but running into this error for a tsmcN65 stack.. Any ideas on what the issue is?
I have a device with an inherited connection for "sub". There is a symbol view with only the inherited pin and a spectre view with a real terminal. When netlisting with the "_ansCdlSubcktCall" netlist procedure, the "sub" pin is never netlisted. Any ideas why or how to get this in the netlist?
My virtuoso:
virtuoso -V
@(#)$CDS: virtuoso version IC23.1-64b 06/21/2023 09:33 (cpgbld16) $
Is there a better way for running multiple analysis? E.g. multiple stb at a specified tran anaylsis time.
Context: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nVpVEAU
And many discusstions on this forum. (Just list some for the sake of future)
Multiple STB on tran
Multiple PAC on PSS:
Multiple noise analysis:
I also have some following questions:
1. if I have more than one ac analysis, will the "VF" function always refer to the default name one? I tried, it seems like is true.
We can find vfreq in the User Guide, but there is not VF. Is VF deprecated? If there are more than one ac analysis, we have to use vfreq function.
What is the difference between "VF("/SIGNAL")" and "vfreq('ac /SIGNAL)"?
(Same question on VT and vtime)
2. Can we do it in ADE Assembler by share transient data between multiple Explorer Tests?
Another work around for the multiple ac analysis is by having multiple Explorer Tests in the ADE Assembler. But if actimes is needed, we have to run multiple tran analysis.
Is there a way to share the data, so that we can have multiple ac analysis and no need to reduplicate tran analysis?
Thank you!
In the module below there is an error that says I cannot assign a real value to a node. How can I solve the issue?
module VA_measureDelay(INPUT_CLOCK,OUTPUT_CLOCK,TIME_DELAY);
input INPUT_CLOCK;
input OUTPUT_CLOCK;
output TIME_DELAY;
electrical INPUT_CLOCK, OUTPUT_CLOCK, TIME_DELAY;
parameter real vdd = 830m;
real time_INPUT_CLOCK, time_OUTPUT_CLOCK;
analog begin
@(cross( V(INPUT_CLOCK)-vdd/2, 1)) begin
time_INPUT_CLOCK = $abstime();
end
@(cross( V(OUTPUT_CLOCK)-vdd/2, 1)) begin
time_OUTPUT_CLOCK = $abstime();
end
TIME_DELAY = time_OUTPUT_CLOCK - time_INPUT_CLOCK;
end
endmodule
Hi,
Here is some info about my current install:
Spectre Version: 21.1.0.isr20 64 bit
Virtuoso Version: ICADVM20.1-64b.500.25
I currently use the Spectre APS simulator for doing top-level analog verification. The part has a mix of full-analog and systemverilog instances. I use ADE Assembler with the ams simulator to run my testbenches. After discovering Spectre X, I decided to give it a try on a few testbenches. I enabled Spectre X in the High Performance Simulation settings, and tried it on a multitude of different accuracy presets. I looked at the Netlist and Run Options window and saw that "Enable AMS flexible release matrix" is checked by default.
In every test I performed, the part would act completely erroneously when compared to the results from the Spectre APS simulator. The part would not even startup, and the operating point of several nets were completely off. In Vx and Lx, the simulation would run quickly but not reach any correct operating point. In Mx and below, the timestep would become so small that no progress was made past a few hundred us and eventually it would fail to converge. I'm not sure what troubleshooting steps I should take to try to resolve these issues, and what (if any) changes should be made when performing AMS simulations using Spectre X. Any advice is appreciated.
-Jacob
Negative impedance converters implemented with OpAmps have an I-V curve as shown below: an input voltage may correspond to multiple currents. This is because the state is stable whether the OpAmp is saturated or not. I'm trying to investigate this circuit and would like to get an I-V curve shown as below. I've tried to give an initial condition (0V) to the output of the OpAmp, but it doesn't help in the DC simulation - the OpAmp still saturates to VDD anyway. Is it possible to achieve this in Cadence with Spectre?
iam having some doubts regarding offset voltage calculation of comparators,can you provide the above workshop content please
i have a test and can work well with single Run, Sweeps and corners. However, after defining variables, like finger width, i go with Advanced Optimization.
There are Error - Cannot Set Cdf Values.
ERROR()ADE-6029): Netlisting failed because of errors in callback 'nsc_90mp_mosCB('fw)' associated with param 'fw'
what't wrong with this? How to fix this error ?
I want to create a linear ramp with the vpwl source and transient analysis.
I did set the pairs (Time 1 = 0s, Voltage 1 = 0s) and (Time 2 = 1us, Voltage 2 = 1V) and I expect a linear ramp from the first pair to the second pair. I measure the voltage at the positive terminal of the vpwl source.
Problem: The source does not ramp, the measured voltage remains at 0V.
Spectre Version: 21.1.0.460.isr10 64bit
Virtuoso Version: IC6.1.8-64b.500.27
hi,
my question is:
is there a possibility to generate a pin shape just on e.g. poly with a width smaller than e.g.0.3 ?
i thought i can do it with this:
absSetBinOption( "Core" "ExtractWidthSig" "0.3")
but in the abstract generator i then saw that this is a minimum value, so it is not what i was looking for.
since we have some more of such issues (special requests), it would be great to have a
description of all the existing absSetBinOption functions.
is there one existing ?
best regards,
drosi
Hello,
I would like to ask 2 questions,
thank you in advance
Dear community
I use VCD files in my ADE Explorer test bench to drive some of the digital signals. One signal is a bidirectional data bus, which I will simply call databus<5:0>. The test bench consists of two phases. In the first phase, databus<5:0> is used as input to load some bits into the circuit's internal register. In the second phase, the circuit uses databus<5:0> as output.
Phase 1 works well in my test bench, but in phase 2, I cannot see any change on databus<5:0>. I suppose the problem is that the VCD file continuously drives databus<5:0> in its last state.
Is it possible to "release" a signal after some time? How can I include bidirectional signals?
Below is a (simplified) snipplet of my .info and .vcd file:
info file
.scope my_test_bench.hier 0.in databus[5:0].vih 1.2.vil 0.0.voh 1.0.vol 0.2.trise 0.1.tfall 0.1.alias *[*] *<*>$date
Apr 11, 2024 15:44:50
$end
$version
TOOL: xmsim(64) 20.09-s010
$end
$timescale
1 ns
$end
$scope module my_test_bench $end
$var wire 6 @ databus [5:0] $end
$upscope $end
$enddefinitions $end
$dumpvars#100[...]