I'm getting the following error:

ERROR (ASSEMBLER-1713): You are attempting to run 1481016621 design points in ADE Assembler.  This exceeds a hard limit of 1e+06 on the size of the run.  Reduce the number of points to be run.

I dont recall getting this error before. What changed and how can the limit be overcome? Thanks!

Shriram

Hello,

I created an abstract view of an inverter using the integrated Abstract Generator. The abstract view looks fine. However, when I used File->Export->LEF, it created an LEF with layers that were not used in the layout.

The inverter layout only uses METAL 1. But in LEF, I see non related vias such as M3_M2.

VIA M3_M2s
LAYER VIA23 ;
RECT -0.13 -0.13 0.13 0.13 ;
LAYER METAL3 ;
RECT -0.19 -0.19 0.19 0.19 ;
LAYER METAL2 ;
RECT -0.19 -0.19 0.19 0.19 ;
END M3_M2s

The log also shows warnings about other vias. Did I miss any steps?

WARNING: (OALEFDEF-50039): VIA M1_NPOLY1s: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.
WARNING: (OALEFDEF-50039): VIA M1_PPOLY1s: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.
WARNING: (OALEFDEF-50039): VIA M1_NACTIVEs: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.
WARNING: (OALEFDEF-50039): VIA M1_PACTIVEs: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.
WARNING: (OALEFDEF-50039): VIA M1_SUBs: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.
WARNING: (OALEFDEF-50039): VIA M1_NWELLs: The via uses more than three layers. This via was ignored. Ensure that the vias are correctly defined.

Hello,

I have generated an extracted netlist (Calibre view) for a circuit.

And now I see each device (e.g. MN1) is represented via MMN1, MMN1@2, MMN1@3 ... in the netlist (separated into fingers).

Now to simulate my circuit, do I need to change all my measurement commands?!

Is there a way to run the same measurement commands over the extracted netlist (Calibre view)?!

Note: I am using QRC for extraction.

Thanks!

I am currently working on an project and in an reference I found this VPULSE element with parameters as you can see. But I am not aware of what each of these parameters indicates. So I request the community to help me with this. And also I need what every parameter refers to ?

As the title said. I'm using the auto route in Layout GXL. The CPU usage is always at 100% and the auto route has been running for days with no sign of complete in a short term. However, it's only using one core and the other cores are pretty much not in use at all.

I'm wondering if the auto route can be configured to use multiple cores. Virtuoso version is 6.1.8.

Thanks!

HI!

The default "ExplorerRun.0" is currently locked in ADE Assembler's history, and I don't remember having done that. Problem is that I can't unlock it, and as consequence, I can't run any simulations in ADE Explorer because it can't overwrite ExplorerRun.0.

As you can see, the unlock option is not available. I don't want to create another meastro view, so is there anything else I can do?

Thank you.

Hi,

I'm new to extraction and post-layout simulation. I can extract parasitics and generate "av_extracted" view. I can also do post-layout simulation using ADE-L>Setup>Environment>Switch View List and adding "av_extracted" before "spectre".

However, I want to use a config file for more control over the view for each block. The problem is, when generating the config file, I noticed that the transistors model in my PDK do not have spectre view. Using other views like "auCdl" or "auLvs" will not give me the correct answer in my post-layout simulation.

Any suggestion to solve this issue?

I'm simulating a negative impedance convertor as shown below (the vcvs's gain is set to 100k, and the output range is 0-1.5V, R0 = 10k, R1 = 1k, R2 = 20k):

I swept the voltage at Vin from 0-1.5V and got the result below (Vcm is set to 0.75V):

The result is as expected - it behaves like a -200k resistor in the range of 0.1-1.4V.

However, when I connect another resistor (from analogLib) in series with this block, it behaves weird. 

R0 here is 300k, and I was expecting to get a 100k equivalent resistance (300k-200k=100k) at node Vtest. I got the satisfying result indeed if I set Vtest to 1V and print the DC operating point after running a DC simulation (as shown in the picture above). 

However, if I sweep the voltage at node Vtest, I get a different result - the current flowing into the node is 3.125uA now. Unfortunately, this value matches with the transient simulation, in which I set up a ramp input.

I checked the DC voltage at each node based on the transient simulation, it also makes sense (the circuit is now working out of the expected range of 0.1-1.4V). Does this mean that the simulator might have found 2 solutions for this circuit? Does this mean that the circuit has some kind of 'unstable' behaviour in terms of operating points?

I'm trying to assign a stimuli via the Stimuli Assignment GUI (in order to easily change it between 2 tests using the same testbench schematic) but it seems I'm running into a limitation of the GUI

Once the voltage (or current) sources have been authored, when you want to assign them to pins it seems that you can only assign the plus output of each source to the given pin

The minus output of the source (mentioned as Ref in the "pin assignments" section) is always set to /gnd!

Is there a way to define where the plus AND the minus outputs of a voltage source are tied ? There are several cases where this could be useful.

Since this GUI, in the end, generates a spectre netlist with the sources defined in it, that is technically possible and seems to be a GUI limitation

Thanks

Hi,

I'd like to include a (spectre syntax) simulation file to one of my tests (in ADE Explorer or Assembler), but WITHOUT referring to it by its absolute path

The reason behind this is that all designers here don't have the same paths. Also, I want this file to be part of our data management scheme so that if someone else checks out this testbench, that person will get the simulation file with the checked out package.

It then would sound convenient to place this file somewhere in the /maestro folder (or subfolders) of the testbench I use.

But how can I refer to this location in a relative way, in the Simulations Files Setup GUI ?

My ADE is set up so in a way that the Options / Save / ADE Assembler Results Database Location is "libs"

So all the maestro files go in a /MyCadencePath/libs/lib_name/cell_name/maestro (ADE then automatically suffixes the libs folder with lib_name/cell_name, and that's of course OK with me)

The question is then, how in the Simulations Files Setup GUI can I refer to my  /MyCadencePath/libs/lib_name/cell_name/maestro/spectre_file.scs but by using a relative path and not an absolute one ?

Thank you

Several of my schematics have date/time (version control?) update text on them. It's date/time, then "added this", "changed that".   It's unwanted and I have no idea how I invoked the option.  I can't seem to find any way to remove it. I can't "Q" it, and the "T" option will highlight it, but not allow me to edit or remove it.

How do I remove this text?

Hello,

I am using ICADVM20.1, is there a way to simulate with ADE Explorer GUI a specific design variable sweep set?

For example, I have these variables

Va = 1 2 3.3

Vb = 1.2 2.4 2.8 2.9

In a single run, I need to simulate these combinations only:

{Va=1, Vb=1.2}, {Va=1, Vb=2.4}, {Va=1, Vb=2.9}, {Va=2, Vb=2.4}, {Va=2, Vb=2.8}, {Va=1, Vb=2.9}, {Va=3.3, Vb=1.2}, {Va=3.3, Vb=2.4}, {Va=3.3, Vb=2.8}, {Va=3.3, Vb=2.9}

I am not interested in running the other combinations. This is just an example, my real case is further complicated, but I need to know if this is possible using Explorer GUI.

Many thanks in advance.

Nader Fathy

For our design we need to perform post-processing of a few waveforms using MATLAB, so we set up a matlabexpr in our Maestro testbench.

So far it works for single point simulations, but the expression sometimes fails to evaluate when the simulation is performed over multiple points by sweeping a design variable or parameter. Oddly enough, the first simulation point gets evaluated correctly, but for the last ones it gives an "eval err" as output.

To debug the problem I modified our post-processing MATLAB function to write a log file as a way to determine where the expression fails to evaluate, and it seems that MATLAB is not even started when the outputs of the second simulation point (and all the remaining points) are evaluated as the log file is unmodified after the first successful evaluation.

With sstatus(errsetTrace t) and _stacktrace=50 I could pinpoint that the issue is in an internal ADE function:

However, I'm totally unable to understand what I should try to fix this issue.

It seems to be reproducible all the time. These are the steps to perform to replicate the issue:

1. Launch Virtuoso and open a Maestro view with a matlabexpr.
2. Start a sweep simulation. All the matlabexpr should evaluate correctly.
3. Start a single point simulation. The matlabexpr should still evaluate correctly.
4. Start a sweep simulation. Now, the first evaluation is successful, while the remaining ones fail.

Our MATLAB version is r2023b and we are running Virtuoso Studio IC23.1-64b.ISR2.29

Hello All,

I wish to seek some advice on running STB analysis on the extracted view of the design. Running STB analysis on the schematic works fine where I have a probe instance selected as MOSFET gate terminal I1/M1/G. The same technique gives incorrect results when I use the extracted version of the MOSFET I1/MM1/G.

Hello,

are there special requirements for the line width and substrate thickness? If my line exceeds a certain width, it exhibits non-physical behavior. At least above a certain frequency. Unfortunately I can't find anything about the underlying model in the documentation.

Best Regards

I have an application that is calling external c-code in using verilog-A for a transient circuit simulation. The c-code saves a log file that reports the time steps the simulation sent it, and I've noticed that sometimes the time-steps are negative.

The c-code is tracking the state of a circuit between function calls. I need to know the correct behavior to take when Cadence asks for a negative time step.

Should I run the system backwards in time? i.e. if I have a resistor in series with a capacitor in my c-code, and the resistor is biased so that current flows through the resistor and onto the capacitor, should I remove charge from the cap during a negative time step? Or should I ignore that time step and keep the initial state of my circuit?

What is the solver doing that it needs to take negative time steps, and are they avoidable? 

Thanks!

Hello 

This is a follow-up of a question I posted over a year ago.

See the link here (https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/57031/run-quantus-fails-depending-on-which-account-it-is-being-used-from)

I am trying to pick up the issue from last year, as I did not find a resolution.

I found out that the account (my account) that ran QUANTUS successfully had a file named np_rpoly_conn, under the LVS run folder.

On the other hand, the account that failed in the QUANTUS run did not have a file with the same name  np_rpoly_conn, under the LVS run folder.

Any idea why one LVS produces this one file while the other does not?

Thank you for your time

I am designing a current steering DAC based on technology TSMC 65 nm. I have a technology 65 nm CMOS TSMC in cadence. I asked how can i extract the mismatch technology parameters Avth and Aβ from this technology. I'm so gratefull if someone have these parameter send me a document.

Best Regards

I am using an analog I/O pad library from TSMC180nm. The schematic view is imported from a Spice file. The layout is from a GDS file. 

I attached an example of a pmos showing this issue. In the schematic view, the l and w are set to 0.4u and 54u to match the dimensions in the layout. However, the dimensions become other numbers when running LVS therefore giving LVS errors. 

If I change the dimensions in the schematic, the numbers shown in LVS will also change, but they never match the numbers in the schematic.

Any help is appreciated!

strcat: argument #1 should be either a string or a symbol (type template = "S") - nil

This error seems to come up frequently when trying to run very simple scripts, and now it's come up in multiple scenarios and I'm wondering if there's some larger issue with how our system is installed. Virtuoso version number is IC6.1.8-64b.500.34.

I'm attempting to create scripts to run simulations for parametric sweeps. I created a schematic, set it up in ADE L, and exported it to a .ocn file. If I run that file with load("oceanScript.ocn") from the GUI CIW it works just fine.

To turn it into a parametric sweep, I edit the file and wrap the simulation as a procedure and then run it in a loop. First off, this alone ran into issues, where running it in a foreach loop gives me that strcat error after the first iteration (i.e the simulation runs once, then in the second loop it does not and gives that error), but running it in a for loop works fine. I cannot for the life of me figure out why a foreach loop and for loop would give problems, and where in the code this strcat error is actually happening. I wrote about how I set up this script on my blog, it links to a github repo with the code for this: https://positivefb.com/gm-id-methodology/

I now want to be able to run a similar script from the terminal (to avoid keeping the device testbench open in a window and cluttering things up). Things like noise analysis and process corners would take an immense amount of time to batch run, so I'd like to run smaller more limited simulations for specific dimensions or conditions as I need. So to test it I ran the previous script, which runs fine from the GUI, in the nograph version with the following command

> virtuoso -64 -nograph -restore termtest.ocn -log termtest.log

That gave me the same strcat error. Doing load("termtest.ocn") from the GUI works just fine though. The script doesn't open any GUI elements, it simply runs the sim, outputs to an outfile, then combines it with a CSV created in the previous iteration. I've also tried putting the load command into a text file and running the text file in nograph mode, like was suggested in another thread.

What am I doing wrong here, why does this error constantly come up in so many situations? Thanks in advance!

Script here:

simulator( 'spectre )
design( "/home/sambady/simulation/gmid_dgnfet/spectre/schematic/netlist/netlist" )
resultsDir( "/home/sambady/simulation/gmid_dgnfet/spectre/schematic" )
modelFile(
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "mainlib")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "FET_tt_pre")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "Res_nom")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "MOSCap_nom")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "APMOMCap_nom")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "MIMCap_nom")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "Ind_nom")
'("$SPECTRE_MODEL_PATH/design_wrapper.lib.scs" "DioCap_nom")
)

;Convert constant variables to waves. Final wave will be length of refwave
procedure(
vartowave(var refwave)
varwave0 = ((refwave+1) * var) ;+1 to avoid any divide by zeros
varwave1 = (varwave0 / (refwave+1))
varwave1 ;return variable as a wave with length of refwave
)

;;;;;;;;;;;;;
;Procedure wrapper for simulation generated by ADE
;;;;;;;;;;;;;
procedure(
simsweep( outputfile length_in vsb_in vgs_in )
analysis( 'dc ?saveOppoint t ?param "vds" ?start "10m" ?stop "2.5" ?step "10m" )
desVar( "F" 5 )
desVar( "L" length_in )
desVar( "vds" 1 )
desVar( "vgs" vgs_in )
desVar( "vsb" vsb_in )
desVar( "W" 10u )
envOption(
'analysisOrder list("dc")
)
saveOpPoint( "/MN0" ?operatingPoints "ids vgs vds vbs vgd vth vdsat gm gds gmbs cjd cjs cgg cgd cgs cgb cdg cdd cds cdb csg csd css csb cbg cbd cbs cbb ron id pwr gmoverid ueff vsb gmb vgt vdss self_gain rout vearly ft region" )
temp( 27 )
run()
print("RUNDONE")
vgs = OS("/MN0" "vgs")
vds = OS("/MN0" "vds")
vsb = OS("/MN0" "vsb")
gm = OS("/MN0" "gm")
Id = OS("/MN0" "ids")
gmId = (gm / Id)
Jd = (Id / VAR("W"))
cgg = OS("/MN0" "cgg")
wt = (gm / cgg)
gds = OS("/MN0" "gds")
Avo = (gm / gds)
FoM = (Avo * wt)

length_wave = vartowave( VAR("L") vds ) ;convert length to wave so it can be a filterable column in the data
width_wave = vartowave( VAR("W") vds )

ocnPrint( ?output outputfile ?numberNotation 'engineering ?numSpaces 4 length_wave width_wave vgs vsb gm Id gds cgg gmId Jd wt Avo FoM) ;output DC sweep to temp file
)

resultscsv = outfile( "./dgnfet_gmid.csv" "w") ;Create empty CSV
close(resultscsv)

;;;;;;;;;;;;;
;Create lengths, vsb, and vds to iterate through. Modify this however you want for whatever you need
;;;;;;;;;;;;;
len_list = list( 280e-9 )
for( i 6 7
next = 50e-9 * i
len_list = cons( next len_list )
)
vsb_list = list( 0 ) ;I don't particularly care about body effect right now, I generally neglect it in my designs
vgs_list = nil
for( i 1 2
next = 50e-3 * i
vgs_list = cons( next vgs_list )
)

;;;;;;;;;;;;;
;Loops iterating through each variable, running sim, and saving to CSV. This is the meat of it
;;;;;;;;;;;;;

for( k 1 length(vsb_list)
for( j 1 length(len_list)
for( i 1 length(vgs_list)
tempout = outfile( "./adel_out.out" "w")
simsweep(tempout nthelem(j len_list) nthelem(k vsb_list) nthelem(i vgs_list)) ;simulation run and saved to temporary output file
close(tempout)

system(sprintf(nil "sed -i '2 r ./test.csv' adel_out.out")) ;existing CSV inserted into output file below header
system(sprintf(nil "sed -i '/^[[:space:]]*$/d' adel_out.out")) ;empty lines deleted
system(sprintf(nil "sed -i '1d' adel_out.out")) ;header deleted
system(sprintf(nil "rm -rf ./test.csv")) ;old CSV deleted
system(sprintf(nil "mv ./adel_out.out ./test.csv")) ;new output file renamed as CSV
)
)
)
;;;;;;;;;;;;;

Relevant portion of the log file:

o Simulation started at: 2:13:52 PM, Wed Mar 20, 2024, ended at: 2:13:53 PM, Wed
\o Mar 20, 2024, with elapsed time (wall clock): 201 ms.
\o spectre completes with 1 error, 0 warnings, and 0 notices.
\o Cannot start up spectre.
\o The specified cds.lib while running the simulation via ADE no longer exists.
\o In absence of the design information, name mapping between extracted names and schematic names won't be carried out.
\o WARNING (OCN-6040): The specified directory does not exist, or the directory does not contain valid PSF results.
\o Ensure that the path to the directory is correct and the directory has a logFile and PSF result files.
\o "RUNDONE" You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\o You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\o You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\o You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\o You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\o You must openResults() on a valid psf directory before
\o using this command. Make sure your openResults() worked.
\o Use ocnHelp('results) for more information.
\e *Error* strcat: argument #1 should be either a string or a symbol (type template = "S") - nil
\e *Error* load: error while loading file - "termtest.ocn" at line 99