Hi,

I am doing custom layout in Virtuouso & and for that purpose, I'll define some designs (as per standard cell rules) and instantiate them in the upper level layouts.

Now, when I instantiate any design in layout, I need to manually align their PR boundary for the neighboring cells.

Is there any way to automate this PR boundary aligning process in Virtuoso?

Any help will be greatly appreciated.

Hi,

No matter how many times I check and save, every time I try to generate the netlinst I get the below error. Please help me solve this.  Cadence Virtuoso version: IC6.1.6.500.1

ERROR (OSSHNL-109): The cell view, 'XXXXX_tb/schematic', has been modified since the last extraction.
Re-extract the design (File->Check and Save menu option) for schematic cell views to correct this error.

Thanks

I want to measure the effective capacitance on a particular node of my schematic ("/net1").

I tried two methods:

1. Using the captab nodetonode option in DC analysis, reading the "/net1" to "/net1" total capacitance from Capacitance Table window.

2. Adding a 1V AC source (V0) connected to the node and running AC analysis. Then get the capacitance vs frequency plot from Spectre Calculator
using the formula 1/(2*3.141593*imag(VF("/net1")/IF("/V0/PLUS"))*xval("/net1")). (This is just C = 1/(2*pi*X*f) where X is reactance and f is frequency in Hz).

I cannot understand how to interpret the results, because the AC analysis gives me a frequency-dependent capacitance, while the Capacitance Table gives a single number.

Is the Capacitance Table value supposed to give me capacitance at limit when f approaches 0 Hz from the AC analysis?

The numbers I get are totally different. The AC analysis capacitance ranges from 1 pF to 2 fF for frequency between 1 Hz and 1 THz.

But the captab value is 0.076 fF, which is smaller than all values from the plot (it's split into Variable: 0.076 fF, Fixed: 0.0).

I don't know what is the most accurate way to measure the effective capacitance on node /net1, and whether any of the results I get make sense.

Additional information:
-----------------------------
Simulator: spectre
Version icfb: 5.10.41

Thank you.

HI

I am trying to execute  the following 'mgc_rve_load_setup_file' command in CIW for a batch of cells.( mgc_rve_load_setup_file command is used to generate calibre view from a pex netlist). For that I am using the below skill code.

procedure(pex_list()
mgc_rve_load_setup_file("calibreview_1")
mgc_rve_load_setup_file("calibreview_2")

mgc_rve_load_setup_file("calibreview_3")

mgc_rve_load_setup_file("calibreview_4")

)

I will load the skill file and then the function pex_netlist() is called in CIW window. For smaller cells like flip-flop,inverter etc the calibre view is getting generated.  But if I try to generate the calibre view of a larger cell (example cells with more that 10 flip-flops) the virtuoso is getting crashed. What is causing this crash. Please guide me, is anything wrong with the way skill file is being executed.

Regards
Anand

Hello,

I want to create an abstract view from an existing layout. This abstract view must contain only pins and the prBoundary.

Is there a simple way or tool in cadence to do this?

Dear Cadence forum,

while experimenting with my netlists with respect to the performance of spectre simulations, I found this forum post saying that reducing the parameter value of subcktprobelvl can avoid saving unnecessary terminal currents of hierarchical subcircuits.

I experimented with this and noticed that the numerical results of the Monte-Carlo simulations I made changed (the resulting numbers are different) when I changed subcktprobelvl=2 to subcktprobelvl=0. As I understand, this parameter affects the amount of data that is stored on disk, but does not modify the simulation parameters (like other parameters do, such as method or gmin). This leaves me confused: Why does a parameter that is supposed to configure result storage have an effect on the numbers that come out?

I am using spectre on the command line (without Virtuoso):

$ spectre -W
sub-version  11.1.0.509.isr14

I created a distilled "sample" netlist that reproduces the problem. The file "corners.scs" included in the netlist references a STMicroelectronics 65nm technology.

simulator lang=spectre
global 0 vdds! gnds! vdd!
include "corners.scs"

subckt inv A Z inh_gnd inh_gnds inh_vdd inh_vdds
parameters nmos_aspect_ratio pmos_scale_factor=2.2
M0 (Z A inh_vdd inh_vdds) psvtlp w=pmos_scale_factor*nmos_aspect_ratio*0.06 l=0.06 nfing=1 mult=1 srcefirst=1 ngcon=1 mismatch=1 lpe=0 dnoise_mdev=0 dmu_mdev=0 dvt_mdev=0
M1 (Z A inh_gnd inh_gnds) nsvtlp w=nmos_aspect_ratio*0.06                   l=0.06 nfing=1 mult=1 srcefirst=1 ngcon=1 mismatch=1 lpe=0 dnoise_mdev=0 dmu_mdev=0 dvt_mdev=0
ends inv

parameters g_nmos_aspect_ratio=10.0
parameters g_pmos_scale_factor=2.2
parameters g_cload=100f
parameters g_risefall=10p
parameters g_dcvoltage=1.200000

// supply
V0 (vdd!      0) vsource dc=g_dcvoltage type=dc
V1 (vdds! gnds!) vsource dc=g_dcvoltage type=dc
R0 (gnds! 0) resistor r=1m isnoisy=no

// test signal
//
// t/ns    0  100 200
//         | . | . | 
//            ___    
// in_s    __/   \__
// 
Vin (in_s 0) vsource dc=0 type=pulse val0=0 val1=g_dcvoltage period=200n delay=50n rise=g_risefall fall=g_risefall width=100n
I0 (in_s out_s 0 gnds! vdd! vdds!)   inv nmos_aspect_ratio=g_nmos_aspect_ratio pmos_scale_factor=g_pmos_scale_factor
Cload (out_s 0) capacitor c=g_cload

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27.000000 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-13 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="./psf/sens.output" \
    checklimitdest=psf
mc1 montecarlo numruns=10 seed=12345 variations=mismatch sampling=standard \
    donominal=no scalarfile="../monteCarlo/mcdata" \
    paramfile="../monteCarlo/mcparam" saveprocessparams=yes \
    savemismatchparams=yes mismatchparamfile="../monteCarlo/mismatchParam" mismatchscalarfile="../monteCarlo/mismatchData" \
    processparamfile="../monteCarlo/processParam" \
    processscalarfile="../monteCarlo/processData" savefamilyplots=no {
tran tran stop=200n write="./psf/spectre.ic" writefinal="./psf/spectre.fc" \
    annotate=status maxiters=5 method=trap

export falltime=oceanEval("delay(\
    ?wf1 getData(\"out_s\" ?result \"tran\") ?value1 0.9*1.200000 ?edge1 'falling ?nth1 1 ?td1 50n \
    ?wf2 getData(\"out_s\" ?result \"tran\") ?value2 0.1*1.200000 ?edge2 'falling ?nth2 1 ?td2r0 50n \
    ?stop nil ?multiple nil)")
export risetime=oceanEval("delay(\
    ?wf1 getData(\"out_s\" ?result \"tran\") ?value1 0.1*1.200000 ?edge1 'rising ?nth1 1 ?td1 150n \
    ?wf2 getData(\"out_s\" ?result \"tran\") ?value2 0.9*1.200000 ?edge2 'rising ?nth2 1 ?td2r0 150n \
    ?stop nil ?multiple nil)")

export delay_fallingoputput=oceanEval("delay(\
    ?wf1 getData(\"in_s\" ?result \"tran\") ?value1 0.5*1.200000 ?edge1 'rising ?nth1 1 ?td1 50n \
    ?wf2 getData(\"out_s\" ?result \"tran\") ?value2 0.5*1.200000 ?edge2 'falling ?nth2 1 ?td2r0 50n \
    ?stop nil ?multiple nil)")
export delay_risingoutput=oceanEval("delay(\
    ?wf1 getData(\"in_s\" ?result \"tran\") ?value1 0.5*1.200000 ?edge1 'falling ?nth1 1 ?td1 150n \
    ?wf2 getData(\"out_s\" ?result \"tran\") ?value2 0.5*1.200000 ?edge2 'rising ?nth2 1 ?td2r0 150n \
    ?stop nil ?multiple nil)")

export crossvoltage_fallingoutput=oceanEval("value(intersect(getData(\"in_s\" ?result \"tran\") getData(\"out_s\" ?result \"tran\")) 0)")
export crossvoltage_risingoutput=oceanEval("value(intersect(getData(\"in_s\" ?result \"tran\") getData(\"out_s\" ?result \"tran\")) 1)")
}
saveOptions options save=allpub subcktprobelvl=2

I created the same netlist with the only difference being the subcktprobelvl parameter:

$ diff level_0/input.scs level_2/input.scs 
67c67< saveOptions options save=allpub subcktprobelvl=0
---> saveOptions options save=allpub subcktprobelvl=2

The results from the OCEAN expressions, as stored in the files named mcdata, are different:

$ diff level_0/monteCarlo/mcparam level_2/monteCarlo/mcparam 
$ diff level_0/monteCarlo/mcdata level_2/monteCarlo/mcdata  
1,10c1,10< 3.75671e-10 3.85534e-10 1.91515e-10 1.8117e-10 1.19625 0.00450162 < 3.70535e-10 3.77426e-10 1.88768e-10 1.77268e-10 1.19583 0.00508238 < 3.9898e-10 3.79619e-10 2.00802e-10 1.78006e-10 1.19758 0.00514946 < 3.75885e-10 3.81322e-10 1.91951e-10 1.79069e-10 1.19653 0.00486543 < 3.78338e-10 3.89232e-10 1.92815e-10 1.82674e-10 1.19638 0.00438965 < 3.75745e-10 3.78624e-10 1.91937e-10 1.77619e-10 1.19659 0.00515173 < 3.78653e-10 3.69747e-10 1.93295e-10 1.73545e-10 1.1967 0.00571527 < 4.02996e-10 3.81731e-10 2.01757e-10 1.79157e-10 1.19745 0.00490435 < 3.91684e-10 3.83e-10 1.97172e-10 1.80602e-10 1.197 0.00435559 < 3.7777e-10 3.74312e-10 1.92494e-10 1.75773e-10 1.19636 0.00532838 
---> 3.8052e-10 3.85254e-10 1.92651e-10 1.8159e-10 1.1999 0.000852351 > 3.74567e-10 3.77439e-10 1.89568e-10 1.77275e-10 1.19966 0.00121274 > 3.98463e-10 3.8045e-10 2.04844e-10 1.7814e-10 1.2 0.00125012 > 3.80442e-10 3.81592e-10 1.93164e-10 1.79424e-10 1.2 0.00108245 > 3.83699e-10 3.90274e-10 1.9411e-10 1.83726e-10 1.2 0.000768679 > 3.80214e-10 3.79212e-10 1.93152e-10 1.77677e-10 1.2 0.00125574 > 3.83735e-10 3.69479e-10 1.94674e-10 1.72791e-10 1.2 0.00161701 > 4.00954e-10 3.82288e-10 2.05985e-10 1.79522e-10 1.2 0.0010966 > 3.91888e-10 3.80556e-10 2.00957e-10 1.80933e-10 1.2 0.000795901 > 3.83069e-10 3.74182e-10 1.93744e-10 1.75474e-10 1.19999 0.00136871 

Note that the two means are quite close to each other while the variances are off by a factor of roughly 1.7:

>>> from numpy import mean, var>>> mean([3.75671e-10, 3.70535e-10, 3.9898e-10, 3.75885e-10, 3.78338e-10, 3.75745e-10, 3.78653e-10, 4.02996e-10, 3.91684e-10, 3.7777e-10])
3.8262569999999997e-10>>> mean([3.8052e-10, 3.74567e-10, 3.98463e-10, 3.80442e-10, 3.83699e-10, 3.80214e-10, 3.83735e-10, 4.00954e-10, 3.91888e-10, 3.83069e-10])
3.8575509999999996e-10>>> var([3.75671e-10, 3.70535e-10, 3.9898e-10, 3.75885e-10, 3.78338e-10, 3.75745e-10, 3.78653e-10, 4.02996e-10, 3.91684e-10, 3.7777e-10])
1.1095435361000017e-22>>> var([3.8052e-10, 3.74567e-10, 3.98463e-10, 3.80442e-10, 3.83699e-10, 3.80214e-10, 3.83735e-10, 4.00954e-10, 3.91888e-10, 3.83069e-10])
6.5714590489999961e-23>>> 1.1095435361000017e-22/6.5714590489999961e-23
1.6884279850588815

My first (and only) idea was that subcktprobelvl could affect the random number generation; I had used the option savemismatchparams=yes to save the random parameters of all transistors, and compared them. They are equal.

$ diff level_0/monteCarlo/mismatchParam level_2/monteCarlo/mismatchParam
$ diff level_0/monteCarlo/mismatchData level_2/monteCarlo/mismatchData

At this point, I have no clue what is happening. Did I do anything wrong or miss any detail in how the netlist is set up? And (in general) how much can I trust the results?

Thank you very much in advance for your help!
Best regards,
Michael Weiner

I'm using Virtuoso Abstract Generator , version  IC6.1.6-64b.500.14 . When trying to run step pins for the cells, I got this warning:

> *WARNING* (ABS-12042): Cell NAND2X1: Design contains zero-pin terminals. There terminals will be deleted.

>INFO (ABS-12001): Cell NAND2X1: There are 5 existing terminals.No pins will be added for them.

>INFO (ABS-11901): Cell NAND2X1: step pin finished.

and pin checking is not successful. I checked the design couple of time and all the pins have proper terminal and pin name. I also generate abstract for INVX0 and INVX1 cells and they work out just fine. 

What could be the possible mistakes here?  How could I solve this? 

Thank You 

Please help me with this issue, When I ran LVS in my design i see this message, I am tried to solve this issue.( Design FinFet 18nm design process).Please help me fixed this issue.

I'm using XL layout on a layout that was initially created in L and has no connectivity source.

Most of the layout work for this cell has been completed in L with no connectivity, so, I'm just using XL to create some nets within the already-completed-layout region (by assigning a net name in the Connectivity tab of the Edit Properties form for a shape in the completed area), and add some instance pins from the not-yet-laid-out region (using Connectivity -> Assign) to those nets, to get the flight lines and drag lines.

This is a big help, but, how can I remove an instance pin from a net, i.e. in case I screw up during the assignment?

Hello,

I am trying to run an OCEAN-XL as an extension using ADE-XL. The way I've been trying to do this is by right-clicking on the ADE-XL output list and "add OCEAN script", but I find that it is not run as part of the Testbench. I can't seem to find information regarding how to setup this an OCEAN script to be invoked by ADE-XL. Any assistance and/or explanation regarding this topic would be highly appreciated

For this case, we are starting with a layout mostly done in L that has pcells but has no nets at all.

In XL, when using Connectivity -> Nets -> Assign to assign an instance pin to a net, the desired target (i.e. the second thing that it prompts you to click) is a shape or another instance terminal that has no net.  In other words, "we want to connect this pin on this pcell resistor to this other simple connectivity-free piece of metal over here."  Apparently, in the Assign command, the target has to be (a shape or via on) an existing net.

While VLS does make it easy to assign a net to the target before running Assign (set the net property on the target shape/via, or add a label and Extract Layout, etc), in this case, we don't really care what VLS thinks the net name is - we just want to see the flight and drag lines.

Is there a way to have Assign automatically create an arbitrary net with a unique net name on the clicked target, which would get rid of the need to take steps to make sure the target is a net before running Assign?

Hello guys,

I have used AMS CMOS 0.35um design kit 4years before, but I forgot how to open Cadence now. Does anyone know?

For example, 

-csh

-(what is here?)

-virtuoso & (or ams?)

Thanks in advance.

Best regards，

UUinfini

So I routinely create libraries where we release it as an IP, with only layout, symbol, spectre and auCdl views for the customer to access.

The spectre and auCdl views have CDF parameters such as model, termorder, etc pointing to external files/netlist the customer can include to run simulations or export CDL of larger blocks,  integrating cells frrom our library. 

Periodically I run into a problem where:

 1. I have create a cell, many times copying it from another cell that is similar, and making a few custom edits.  I usually have to edit the CDF parameters to match as well, primarily fixing termorder and the model name parameter so the specre/auCdl views points to the correct model in the external include files.

2. BUT...Every time I reload virtuoso, all of the cdf parameters of this one (or possibly multiple cells) revert back to original settings or older CDF parameters.  As if they were never changed.

No matter how many times I change the parameters, apply and save, they are only good as long as I do not close that virtuoso session, but once I close it and then reopen it, it is as if I never changed them in the first place. 

I have gone into the database, I do not see any obvious files like lock files blocking the saving of the parameters, but, I am still at a loss.

Any suggestions would be appreciated.

 Regards

Hello all,

I am working on a project where use a number of std filler cells. In LVS, these filler cells gave parameter missmatches, with the warning of ambiguous cells in the design.

So I adjusted the Ambiguity Threshold to the suggested number, and LVS passed. Nice!

But: What is this?
I looked documentation, but all I found was how to adjust this threshold (In GUI mode: LVS Options - Comparison Options Tab - Breaking Ambiguity Threshold).

What does it affect? Is there any downside (apart from LVS speed) to have a higher ambiguity threshold?

I am glad for any information about this - Thank you very much!

Adrian

I'm trying to understand what options, if any, I might have for controlling what different combinations of layers, widths, and spacing are used in a "Techgen -simulation" run.  This is EXT17.12.  Also if I am only planning on running Quantus-FS (field solver mode) and not the "full chip" mode (QRC), is there a way to dramatically speed up the Techgen -simulation stage?

I'm currently running:

Techgen -simulation -multi_cpu 8 -cell_off myprocess.ict

so far what I'm seeing is I wish I had the hardware to make that 8 about 128!

Thanks

-Dan

Hello,

I would like to have 2 adexl views and I would like to create a copy of the first adexl view without the History. The reason is that I want to simulate at the same time with two different servers, so I need a adexl that is not locked while the other one is running.

If I just copy-paste the first adexl, I get the History (saved in server1), but this is annoying because from server 2 I cannot access that history. Therefore I would like to create a copy with all the settings, but the history of the copied adexl view should be empty.

Do you know a way to do it?

Thanks 

Hello, I'm stuck with an error in my simulation that prevents me to see any results.

I have a system with one digital block (Verilog) and several analog blocks. I'm using the extracted views (with Calibre Pex) for my analog blocks. I use Cadence Virtuoso 6.1.7 and AMS Unified Netlister with irun. I would like to run a parametric simulation for a few values of the input digital codes of my Verilog block. For each code I run a dc simulation and then a transient.

Unfortunately, I get a red message: sim err  for each simulation. The netlist seems ok. I looked at irun.log and Job Log.

- irun.log shows an error in transient. I copy here what I get.

******************
DC Analysis `dcOp'
******************
Important parameter values:
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
gmindc = 1 pS
rabsshort = 1 mOhm
Convergence achieved in 2 iterations.
Total time required for dc analysis `dcOp': CPU = 163.873 s (2m 43.9s),
elapsed = 51.1972 s.
Time accumulated: CPU = 17.907 ks (4h 58m 27s), elapsed = 8.22368 ks (2h 17m
4s).
Peak resident memory used = 24.5 Gbytes.

************************************************
Transient Analysis `tran': time = (0 s -> 25 ns)
************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
There are 2 IC nodes defined.

Finding DC approximate solution failed. Try again with try_fast_op set to no.
Trying `homotopy = gmin' for initial conditions.

Trying `homotopy = source' for initial conditions.

- Job Log gives me this error message:

INFO (ADEXL-1654): Simulator 'ams' doesn't provide simulation failure
\o information at the analysis level. So 'SkipFailedAnalyses' for option
\o 'evalOutputsOnSimFailure' wouldn't work for this simulator.
\o
\o *Error* Error ID = 5011
\o *Error* Error Msg = Simulator failed to complete the simulation.
\o
\o The simulator process returned a non-zero exit code 137,
\o indicating failure.
\o The simulator could have crashed or
\o intentionally returned to indicate an error.
\o Check the
\o simulator log file for more information. Common causes:
\o 1.
\o Simulator may have crashed during exit even after reporting
\o success in log file.
\o 2. Abrupt automatic simulator
\o termination (e.g., SIGKILL) because the simulator process
\o has
\o exceeded resource limits, which can be specified in
\o the distribution system or
\o by the kernel itself (e.g.,
\o the Linux OOMKiller).
\o 3. Manual termination of the
\o simulator process.
\o ./runSimulation can be manually run in
\o this directory to check the issue.

Both these messages are quite generic and I could not identify the cause of my error. I managed to run the same simulation with schematic views for my analog blocks, but I get these errors when I switch the view to the extracted ones. Could you please suggest me where to look to understand the problem? I need to check my extracted system

Thanks a lot

HI ,

I am trying to generate LEF file of an abstract (top level cell: TOP_CELL). Eventhough LEF is getting generated it is missing the following information.

###################################################
CLASS;
Symmetry ;
SIZE X Y;
FOREIGN TOP_CELL_NAME (0 0) N

ORIGIN (0 0);

#######################################

I am using LEF Version: 5.7
Virtuoso: IC6.1.7-64b.500.7

options  enabled in LEF generation menu window are

1) LEF File Name:  TOP_CELL.lef

2)cells

3)Output cell(s): TOP_CELL

4)Output views : abstract

5) Lef version: 5.7
6)No Technology

7)Generate cell list by: Cells in Design

8)Use GUI Fields

Is there anything wrong in the way LEF is being generated ?.  I am seeing the pin information and blockage layer information  available in the LEF file that was generated.



Regards
Anand

Hi,

I am working on Virtuoso, version IC6.1.7-64b.500.4. I am using inherited connections in the schematic. AFter parasitic extraction, I observe that the inherited connections are missing in the netlist. I know that it is not recommended to use inherited netlist. Still, is it possible to have a work around so that with the inherited connections we can have a symbol with all the power\ground pins?

thanks in advance.

Saikat Chatterjee

I've been looking in to how I can get multiple machines involved in a Techgen run.  I read the DPL  User Guide and it suggests some command line utilities for verifying the DPL config file (dplCfgValidator) and for testing the cluster (dplDiagCmdUtil).  However, when I try either of these I get a "DPL applications required Run DPL using a application" message.  I can't see where the manual says anything about this.  

> /opt/eda/cadence/EXT171/bin/dplCfgValidator -ConfigFile dp_config.xml
DPL applications required Run DPL using a application

>

Here is a version:

-----------------------------------------------------------------
Name : dplCfgValidator - Cadence DPL Engine - (64-bit)
Description : Cadence Shared Technology for Distributed Computing
Version : 8.3.3-a001
Build Ref. No. :
IR Build No. : Engineering build
Build Date : (01/19/2017 19:46:16)
-----------------------------------------------------------------

The other thing which wasn't clear in the manual was the relationship between <Host> tags in the XML DPL config file and the -dp_num command line argument.  Is there a way to tell the tool "just use all of the hosts" or do I need to count my hosts and use that as the argument to -dp_num?  The other thing which wasn't clear is the DPL config file lets me specify a number of jobs per host like:

<Host instance="8">host1</Host>

<Host instance="4">host2</Host>

so in this case do I use -dp_num 2 (for two hosts) or do I use -dp_num 12 (to get all slots on all machines)?

If it matters, I'm using <DPLEnvironment type="ssh">