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Nested equations in ADEL

October 13, 2017, 3:22 am
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Hi, 

I want to compute the time elapsed between the falling edge of two signals. I've used cross() to get the time at which each event occurs, and it works. The problem is that when I try to compute the difference between the two, I get the error: *Error* ("difference" 0 t nil ("*Error* difference: can't handle ((.....) -(......)).

Searching in past threads, I found that the issue is related to the nested parenthesis. The problem is that I've tried both using variables, putting cross() function in an output of ADEL, let's  say t1 and t2, and making the difference t1-t2, or writing a single equation: cross(sig1)-cross(sig2), but it looks like the parenthesis are added automatically and I still get the same error. 

Any suggestion? 

I'm using version 6.1.7

Thank you in advance!

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Invalid probe for a .measure statement where node also exist as port in one hierarchy above

October 13, 2017, 3:27 am
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Hello All,

Consider the following node in a .measure statement
V(segio.segio0.controls.xcontrols_opt/RDWEN_T)

Now when
1) RDWEN_T is signal above statement works.
2) when RDWEN_T is port is gives invalide probe. when I checked out in waveform viewever this port is there one hierarchy above(same same).

So what option I should use to make simulator understand ?

Thanks.

Using spectre-xps simulator

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LVS shows "StampErrorMult" error

October 15, 2017, 2:40 am
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I'm designing a current source layout in Virtuoso 6.1.6.-64b

My circuit contain mim capacitors, NWELL diffusion resistor along with 1.8V NMOS and CMOS. when I ran LVS, it provides this three error:

> n_psub_StampErrorMult

>psub_term_StampErrorMult

>psub_StampErrorMult

I dont have clear idea what this errors mena. Tried to google it, but found no useful information. I checked couple of times in my layout to find any short or floating body. I do not find any. Could you explain me about the error and possible ways to solve this.

thank you

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IC617 layout slow in VNC

October 17, 2017, 8:35 am
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We recently updated from IC616 to IC617 (IC6.1.6-64b.500.14) and have felt like the interactive performance of virtuoso layout-L, even in read-only mode, has suffered.  We exclusively access the eda machines with VNC (tiger VNC).  In fact we do not have physical access to any machines that directly run the tools.  I've observed that Xvnc CPU usage (in top) will jump to 100% quite easily when trying to zoom/pan a large layout.  We've not changed anything else that I'm aware of in terms of OS, hardware, network, software other than the IC616 to IC617 switch.  Anyone have good trouble shooting ideas on how to get to the bottom of the issue and hopefully get the speed back?

Thanks

-Dan

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String variable as node name in mdl file?

October 17, 2017, 11:52 am
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Hello,

I wonder if it is possible to substitute a node name in mdl file using a sting variable. e.g.:

alias measurement meas1 {

input string myNodeName = "comp0.Q" 

export real vQ=V(myNodeName)@1n

}

Thanks and regards,

Ioannis

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ERROR (VACOMP-1008)

October 18, 2017, 6:58 am
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Hi!

During simulations I have found these two errors in the log file (I'm trying to simulate a verilog-A component):

ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//47c64761172b7ee38fd8b848ec102865.resistor_v1.ahdlcmi/Linux-64//..//ahdlcmi.out for details. Contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.

ERROR (SFE-91): Error when elaborating the instance resistor_v1. Simulation should be terminated.

Also there are two warnings:

WARNING (VACOMP-2435): The environment variable CDS_AHDLCMI_ENABLE is no longer supported. Therefore, the simulator will use the default compiled C code flow.

(This one is because I have set CDS_AHDLCMI_ENABLE as "export CDS_AHDLCMI_ENABLE=NO"... I have read on Internet that maybe this sentence could solve the problem...Either way the simulation doesn't work)

WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

I attach the ahdlcmi.out file. In addition, I provide the following data:

  • Spectre -W: sub-version 15.1.0.627.isr12
  • Uname -a: Linux simulation-server 4.2.0-42-generic #49-Ubuntu SMP Tue Jun 28 21:26:26 UTC 2016 x86_64 x86_64 x86_64 GNU/Linux

The command cat /etc/redhat-release gives an error (No such file or directory)

Can anybody help me to solve this problem? Any idea? I would very much appreciate.

Best regards,

Irene

(Please visit the site to view this file)

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Body Connection for 18nm process finfet

October 18, 2017, 7:24 am
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hi everyone,

I want to design layout by finfet 18nm process but I could not find tap cell ( well tap & substrate tap).So I want to make own tap cell for body connection but I don't know layer type or which layer use for tap cell in 18nm process.

I was working 45nm,90nm & 180nm.But I am new 18nm process.So please anyone help me about this issue.

thnaks

Jonaeath Hossin

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How to open Cadence using C35B4 design kit

October 18, 2017, 9:25 pm
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Hello guys,

I have used C35B4 design kit 4years before, but I forgot how to open Cadence. Anyone knows?

For example, 

-csh

-(what is here?)

-virtuoso & (or ams?)

Thanks in advance.

Best regards，

UUinfini

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CDF parameters constantly revert back to prior settings

October 24, 2017, 3:01 pm
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So I routinely create libraries where we release it as an IP, with only layout, symbol, spectre and auCdl views for the customer to access.

The spectre and auCdl views have CDF parameters such as model, termorder, etc pointing to external files/netlist the customer can include to run simulations or export CDL of larger blocks,  integrating cells frrom our library. 

Periodically I run into a problem where:

 1. I have create a cell, many times copying it from another cell that is similar, and making a few custom edits.  I usually have to edit the CDF parameters to match as well, primarily fixing termorder and the model name parameter so the specre/auCdl views points to the correct model in the external include files.

2. BUT...Every time I reload virtuoso, all of the cdf parameters of this one (or possibly multiple cells) revert back to original settings or older CDF parameters.  As if they were never changed.

No matter how many times I change the parameters, apply and save, they are only good as long as I do not close that virtuoso session, but once I close it and then reopen it, it is as if I never changed them in the first place. 

I have gone into the database, I do not see any obvious files like lock files blocking the saving of the parameters, but, I am still at a loss.

Any suggestions would be appreciated.

 Regards

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Ambiguity Threshold in PVS-LVS

October 25, 2017, 12:51 am
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Hello all,

I am working on a project where use a number of std filler cells. In LVS, these filler cells gave parameter missmatches, with the warning of ambiguous cells in the design.

So I adjusted the Ambiguity Threshold to the suggested number, and LVS passed. Nice!

But: What is this?
I looked documentation, but all I found was how to adjust this threshold (In GUI mode: LVS Options - Comparison Options Tab - Breaking Ambiguity Threshold).

What does it affect? Is there any downside (apart from LVS speed) to have a higher ambiguity threshold?

I am glad for any information about this - Thank you very much!

Adrian

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Controlling combinations in Techgen / Techgen for Quantus-FS only?

October 25, 2017, 7:28 am
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I'm trying to understand what options, if any, I might have for controlling what different combinations of layers, widths, and spacing are used in a "Techgen -simulation" run.  This is EXT17.12.  Also if I am only planning on running Quantus-FS (field solver mode) and not the "full chip" mode (QRC), is there a way to dramatically speed up the Techgen -simulation stage?

I'm currently running:

Techgen -simulation -multi_cpu 8 -cell_off myprocess.ict

so far what I'm seeing is I wish I had the hardware to make that 8 about 128!

Thanks

-Dan

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Copy adexl view without history

October 28, 2017, 6:50 am
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Hello,

I would like to have 2 adexl views and I would like to create a copy of the first adexl view without the History. The reason is that I want to simulate at the same time with two different servers, so I need a adexl that is not locked while the other one is running.

If I just copy-paste the first adexl, I get the History (saved in server1), but this is annoying because from server 2 I cannot access that history. Therefore I would like to create a copy with all the settings, but the history of the copied adexl view should be empty.

Do you know a way to do it?

Thanks 

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error in AMS simulation

October 30, 2017, 2:27 am
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Hello, I'm stuck with an error in my simulation that prevents me to see any results.

I have a system with one Verilog block, plus I'm using the extracted views (with Calibre Pex) for my analog blocks. I use Cadence Virtuoso 6.1.7 and AMS Unified Netlister with irun. I would like to run a parametric simulation for a few values of the input digital codes of my Verilog block. For each code I run a dc simulation and then a transient.

Unfortunately, I get a red message: sim err  for each simulation. The netlist seems ok. I looked at irun.log and Job Log.

- irun.log shows an error in transient. I copy here what I get.

******************
DC Analysis `dcOp'
******************
Important parameter values:
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
gmindc = 1 pS
rabsshort = 1 mOhm
Convergence achieved in 2 iterations.
Total time required for dc analysis `dcOp': CPU = 163.873 s (2m 43.9s),
elapsed = 51.1972 s.
Time accumulated: CPU = 17.907 ks (4h 58m 27s), elapsed = 8.22368 ks (2h 17m
4s).
Peak resident memory used = 24.5 Gbytes.


************************************************
Transient Analysis `tran': time = (0 s -> 25 ns)
************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
There are 2 IC nodes defined.

Finding DC approximate solution failed. Try again with try_fast_op set to no.
Trying `homotopy = gmin' for initial conditions.

Trying `homotopy = source' for initial conditions.

- Job Log gives me this error message:

INFO (ADEXL-1654): Simulator 'ams' doesn't provide simulation failure
\o information at the analysis level. So 'SkipFailedAnalyses' for option
\o 'evalOutputsOnSimFailure' wouldn't work for this simulator.
\o
\o *Error* Error ID = 5011
\o *Error* Error Msg = Simulator failed to complete the simulation.
\o
\o The simulator process returned a non-zero exit code 137,
\o indicating failure.
\o The simulator could have crashed or
\o intentionally returned to indicate an error.
\o Check the
\o simulator log file for more information. Common causes:
\o 1.
\o Simulator may have crashed during exit even after reporting
\o success in log file.
\o 2. Abrupt automatic simulator
\o termination (e.g., SIGKILL) because the simulator process
\o has
\o exceeded resource limits, which can be specified in
\o the distribution system or
\o by the kernel itself (e.g.,
\o the Linux OOMKiller).
\o 3. Manual termination of the
\o simulator process.
\o ./runSimulation can be manually run in
\o this directory to check the issue.

Both these messages are quite generic and I could not identify the cause of my error. I managed to run the same simulation with schematic views for my analog blocks, but I get these errors when I switch the view to the extracted ones. Could you please suggest me where to look to understand the problem? I need to check my extracted system

Thanks a lot

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LEF generation from abstract is missing class,symmetry, origin information

October 30, 2017, 4:06 am
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HI ,

I am trying to generate LEF file of an abstract (top level cell: TOP_CELL). Eventhough LEF is getting generated it is missing the following information.

###################################################
CLASS;
Symmetry ;
SIZE X Y;
FOREIGN TOP_CELL_NAME (0 0) N

ORIGIN (0 0);

#######################################


I am using LEF Version: 5.7
Virtuoso: IC6.1.7-64b.500.7

options  enabled in LEF generation menu window are

1) LEF File Name:  TOP_CELL.lef

2)cells

3)Output cell(s): TOP_CELL

4)Output views : abstract

5) Lef version: 5.7
6)No Technology

7)Generate cell list by: Cells in Design

8)Use GUI Fields


Is there anything wrong in the way LEF is being generated ?.  I am seeing the pin information and blockage layer information  available in the LEF file that was generated.



Regards
Anand

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Creating all pin symbol containing inherited power\ground connections

October 30, 2017, 9:14 am
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Hi,

I am working on Virtuoso, version IC6.1.7-64b.500.4. I am using inherited connections in the schematic. AFter parasitic extraction, I observe that the inherited connections are missing in the netlist. I know that it is not recommended to use inherited netlist. Still, is it possible to have a work around so that with the inherited connections we can have a symbol with all the power\ground pins?

thanks in advance.

Saikat Chatterjee

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Distributed Processing Library command line

October 30, 2017, 12:29 pm
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I've been looking in to how I can get multiple machines involved in a Techgen run.  I read the DPL  User Guide and it suggests some command line utilities for verifying the DPL config file (dplCfgValidator) and for testing the cluster (dplDiagCmdUtil).  However, when I try either of these I get a "DPL applications required Run DPL using a application" message.  I can't see where the manual says anything about this.  

> /opt/eda/cadence/EXT171/bin/dplCfgValidator -ConfigFile dp_config.xml
DPL applications required Run DPL using a application

>

Here is a version:

-----------------------------------------------------------------
Name : dplCfgValidator - Cadence DPL Engine - (64-bit)
Description : Cadence Shared Technology for Distributed Computing
Version : 8.3.3-a001
Build Ref. No. :
IR Build No. : Engineering build
Build Date : (01/19/2017 19:46:16)
-----------------------------------------------------------------

The other thing which wasn't clear in the manual was the relationship between <Host> tags in the XML DPL config file and the -dp_num command line argument.  Is there a way to tell the tool "just use all of the hosts" or do I need to count my hosts and use that as the argument to -dp_num?  The other thing which wasn't clear is the DPL config file lets me specify a number of jobs per host like:

<Host instance="8">host1</Host>

<Host instance="4">host2</Host>

so in this case do I use -dp_num 2 (for two hosts) or do I use -dp_num 12 (to get all slots on all machines)?

If it matters, I'm using <DPLEnvironment type="ssh">

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Gain of a Charge Pump in Phase locked loop

October 31, 2017, 9:10 am
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Hi,

I made a charge pump for 1GHz PFD up and down signal pulses. I am interested in finding out the gain of Charge Pump. Can anyone guide me the good reference or some idea about its procedure?

Thanks,

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change instance name in schematic

October 31, 2017, 9:47 am
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It is a very simple question, it seems that I can't change an instance name by "q" it in schematic window. I have to go to the property editor and change it there. For instance, I placed a resistor R1 in the schematic and then later I want to change it to R1<2:0>. Naturally I want to q it and then change it there. however, the instance name field is grey. Instead, I have to change it in the property editor. For some reason, changing things in the property editor can be annoying. I click in the field that I want to change, sometimes when my cursor moves, then immediately the edit mode is gone, I have to click again and again.  I don't know why it is happening.

Is there a way that I can edit the instance name by q it in schematic, or how can I fix the input issue in the property editor? I am using IC617.

Thanks!

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gpdk045 vth at dcop is not same as model spec

November 1, 2017, 6:49 am
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Hi, Andrew

I have checked the gpdk045 model report, it's said the vth is obtained using constant current method, the intercept current=Icon*W/L (Icon=1e-8A for 1.1V device and Icon=1e-7A for 1.8V device), Vth unit is V, spec is here

and i simulated use the circuit, VDS=1.1V and sweep the VGS from 0 to 1.1V.

according to the equation constant current method int current = 10u/40n *1e-8A =2.5*e-6 A =2.5uA, check the ids and vth is located at around 320mV, close to the spec, but check at result browser, plot the vth, about 620mV, what is wrong here? thanks a lot.

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How to determine Scaled-sigma sampling (SSS) Number in high-yield estimation (HYE) for SRAM design? Thanks

November 2, 2017, 1:45 am
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I am running high-yield estimation (HYE) simulation for custom SRAM design in Virtuoso 6.1.6 ADE XL. The simulation circuit is a critical path which contains representative cells and wire delay models to mimic 512Mb SRAM macro. We do not run a simulation directly on the 512Mb SRAM macro to avoid highly long run-time. 

In HYE setup, we need to specify the sampling number for Scaled-sigma sampling (SSS) method. According to Cadence technical paper, the default number of samples for SSS is 7000. 

The problem is, the 512Mb SRAM macro has millions of devices while the critical path has only hundreds of devices. When we run HYE on the critical path, we expect that the hundreds of devices' variations could mimic millions of devices' variations in some way. Assume that the default 7000 sampling number is appropriate for 512Mb SRAM macro's HYE simulation,  then what sampling number is adequate for  the critical path HYE simulation in order to mimic millions of devices' variations?  

Actually, I am not even sure if the default 7000 sampling number is adequate when running HYE simulation directly on the 512Mb SRAM macro.

I appreciate any suggestions on this problem. Thanks and regards.

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