Hello

I am trying to run RelXpert for the first time and I get the following error in the rxprofile.log file :

...

* Netlist file: profile.cfg
* Starting time: Thu Sep 14 16:37:56 2017
*
* Command Line Input: <server>/cadence/MMSIM141/tools.lnx86/relxpert/bin/64bit/rxprofile -ade -raw ../psf -log ../psf/rxprofile.log -out ../psf/.rxprofileMessages.out -spectre_args +escchars -format psfxl +lqtimeout 900 -maxw 5 -maxn 5
*
*****************************************************************************

rxprofile starts: ......

=============================================================================

Warning(RELXP-351): RelXpert statement '.age' in netlist will be ignored, 'use the age value set in the agepoint'.
=================================AGEPOINT: 2y================================
executing "relxpert -pre -profile 1 -agevalue 6.3072e+07 -sp -pre input.scs input.p1>temp.log "...
Error(RELXP-186): The RelXpert simulator failed to perform 'relxpert -pre -profile 1 -agevalue 6.3072e+07 -sp -pre input.scs input.p1>temp.log '. Check the profile option '' before running rxprofile again. Refer to the rxprofile.log file or the RelXpert documentation for more information.

rxprofile failed!(exit status 1)

When checking the temp.log file the Error is:

Error found by spectre during circuit read-in.
ERROR (SFE-874): "input.p1" 95: Unexpected string value "/".
ERROR (SFE-874): "input.p1" 7454: Unexpected string value "dnoin_mc".

Line 95 in input.p1 is 

//*********************************************************************

and line 7454 in input.p1 is:

+ dnoin_mc=0

Do you guys have any suggestion to fix the error?

Thanks!

Patricia 

Hi,

I'm simulating an oscillator with a source input to kick-start the oscillation. I tried to plot the the frequency of the output signal Vs. the control voltage. But I have read several posts saying that it couldn't be done with PSS anlaysis. Instead, it could be done using harmonic balanced simulation (HB) as it has "Semi-autonomous" mode.
I have tried HB analysis several times but there was an error :

No convergence achieved with the minimum time step specified.  Last acceptable solution computed at  0s.How to overcome this error?.

Now, knowing that the circuit works in the range [1-4 GHz] how to set-up the harmonic balance analysis correctly?

I'm using virtuoso 6.1.7
hope anyone could help me.
thanks.

Hi,

I'm trying to pass different transistor lengths/widths to an array of nfet devices MN0<2:0>. I tried passing "[100n 200n 300n]" in the length field of the nfet property window as suggested here: https://community.cadence.com/cadence_technology_forums/f/38/t/20875

but Spectre returns a warning: Invalid value '[100n200n300n]' of type `scalar string' encountered. Expected value is of type `double' and the wrong W/L values are used.

Is there a way of achieving this?

Thanks,

Patrick

Hi,

Could I use cds_get_analog_value to measure an inherited connection port? More specifically I need to measure the current at an inherited connection port using cds_get_analog_value.

Thanks,
Hoang

Hello,

I've got one weird issue with cadence. I am in the ADE-XL environment. When I try to load the corner setup by clicking on 'Click to add corners', Load Corners GUI shows up. 

However, it won't show any folder or sub-folder where the .sdb file is located (please refer to the snapshot in the attachment).  Any idea how to fix this issue?

I am using IC6.1.4.

Thanks

Syafiq

We had a Linux maintenance down over the weekend.  Linux severs were patched as part of the maintenance down.  checkSysConf output prior to patching/maintence down is included below. A new file system was attached. Now virtuoso won't start.  Entire design team is down.  I have also filed a Cadence support request and I'm waiting for a response.

=====================================================================

[Copyright 2002-2016] Cadence Design Systems, Inc. All rights reserved.

This program and online documentation may not be copied, modified,

re-published, uploaded, executed, or distributed in any way, in any

medium, whether in whole or in part, without prior written permission

from Cadence Design Systems, Inc.

=====================================================================

============== checkSysConf: Version 3.25 ====================

Date information gathered: Thu Sep 21 15:05:22 CDT 2017

-------------------------------------------------------

Host Name ..............: ep1p-apca04.starkey.com

Hostid .................: 280a6220

Operating System .......: Linux / x86_64

OS Version .............: Red Hat Enterprise Linux Server release 6.7 (Santiago)

Kernel Version .........: 2.6.32-573.12.1.el6.x86_64

Hardware Type ..........: x86_64

Memory .................: 128793 Megabyte

CPU model ..............: Intel(R) Xeon(R) CPU E5-2670 v3 @ 2.30GHz

No. of CPUs ............: 48

Total Swap Space........: 4095 Megabyte

X Server ...............: [ 31.174] (--) MGA(0): Pseudo-DMA transfer window at 0xC6000000

Patch Data file ........: /cad/apps/cadence/virtuoso_6.1.7.714/share/patchData/Linux/x86_64/redhat/6.0WS/IC6.1.7

**************** Now verifying configuration ****************

Validating Kernel requirements...

Minimum Installed Status Info

-------------- -------------------------- ------ --------------------

2.6.32-431.11.2 2.6.32-573.12.1.el6.x86_64 PASS

Validating MEMORY requirements MegaByte ...

Minimum Installed Status Info

------- --------- ------ --------------------

2048MB 128793MB PASS

Validating SWAP requirements in MegaByte ...

Minimum Installed Status Info

------- --------- ------ --------------------

4096MB 4095MB FAIL

Validating DISPLAY requirements...

Minimum Installed Status Info

----------------- ---------------- ------ ----

8 planes 24 planes PASS

PseudoColor TrueColor

Validating PACKAGE requirements.....29 to check

# PACKAGE Release Build Installed Arch Status Info

-- ------- ------- ----- ---------- ---- ------ --------------------

1 glibc 2.12 1.132 2.12-1.166.el6_7.3 i686 PASS

-> 'GlibC'

2 glibc 2.12 1.132 2.12-1.166.el6_7.3 x86_64 PASS

-> 'GlibC'

3 elfutils-libelf 0.152 1 0.161-3.el6 i686 PASS

-> 'Libelf Library'

4 elfutils-libelf 0.152 1 0.161-3.el6 x86_64 PASS

-> 'Libelf Library'

5 ksh 20120801 10 20120801-28.el6_7.3 x86_64 PASS

-> 'ksh'

6 mesa-libGL 9.2 0.5 - FAIL Package not installed.

-> ----------------------

-> 'Mesa libGL Library'

7 mesa-libGL 9.2 0.5 10.4.3-1.el6 x86_64 PASS

-> 'Mesa libGL Library'

8 mesa-libGLU 9.2 0.5 - FAIL Package not installed.

-> ----------------------

-> 'Mesa libGLU Library'

9 mesa-libGLU 9.2 0.5 10.4.3-1.el6 x86_64 PASS

-> 'Mesa libGLU Library'

10 openmotif22 2.2.3 19 - FAIL Package not installed.

-> ----------------------

-> 'openmotif'

11 openmotif22 2.2.3 19 2.2.3-19.el6 x86_64 PASS

-> 'openmotif'

12 libXp 1.0.0 15.1 - FAIL Package not installed.

-> ----------------------

-> 'libXp'

13 libXp 1.0.0 15.1 1.0.2-2.1.el6 x86_64 PASS

-> 'libXp'

14 libpng 1.2.49 1.el6_2 - FAIL Package not installed.

-> ----------------------

-> 'libpng'

15 libpng 1.2.49 1.el6_2 1.2.49-2.el6_7 x86_64 PASS

-> 'libpng'

16 libjpeg-turbo 1.2.1 1 - FAIL Package not installed.

-> ----------------------

-> 'libjpeg'

17 libjpeg-turbo 1.2.1 1 1.2.1-3.el6_5 x86_64 PASS

-> 'libjpeg'

18 compat-expat1 1.95.8 8 - FAIL Package not installed.

-> ----------------------

-> 'libexpat.so.0'

19 compat-expat1 1.95.8 8 1.95.8-8.el6 x86_64 PASS

-> 'libexpat.so.0'

20 libXtst 1.2.1 2 1.2.2-2.1.el6 i686 PASS

-> 'libXtst.so.6'

21 libXtst 1.2.1 2 1.2.2-2.1.el6 x86_64 PASS

-> 'libXtst.so.6'

22 compat-readline5 5.2 17.1 - FAIL Package not installed.

-> ----------------------

-> 'Readline Library'

23 compat-readline5 5.2 17.1 5.2-17.1.el6 x86_64 PASS

-> 'Readline Library'

24 ncurses-libs 5.7 3.20090208 - FAIL Package not installed.

-> ----------------------

-> 'ncurses library'

25 ncurses-libs 5.7 3.20090208 5.7-4.20090207.el6 x86_64 PASS

-> 'ncurses library'

26 redhat-lsb 4.0 7 - FAIL Package not installed.

-> ----------------------

-> 'lsb'

27 redhat-lsb 4.0 7 4.0-7.el6 x86_64 PASS

-> 'lsb'

28 glibc-devel 2.12 1.132 2.12-1.166.el6_7.3 i686 PASS

-> 'GlibC-devel'

29 glibc-devel 2.12 1.132 2.12-1.166.el6_7.3 x86_64 PASS

-> 'GlibC-devel'

Validating FILE existence .....0 to check

Validating NOTFILE existence .....0 to check

Configuration checks failed on this workstation (ep1p-apca04.starkey.com), status is: FAIL

This system does not have the correct packages to run IC6.1.7

Run checkSysConf IC6.1.7 -P <PACKAGE>

to find out which products require this package.

Exiting checkSysConf ... Good-bye

Output is saved as /tmp/checkSysConf.ep1p-apca04.starkey.com-2017.09.21.15:05.7823.log

Hello to everybody,

Recently I have begun working with Cadence Virtuoso 6.17. When I want to perform an ADE-L simulation I obtain the following error in the CIW:

ERROR (ADE-3023):Cannot run simulations because the spectre executable is not found in the specified 'UNIX $PATH' setting.
Perform the following steps to specify the simulator executable path:
1.Download and install the required tool version from http://downloads.cadence.com:
- For analog simulations, download and install MMSIM
- For AMS simulations, download and install INCISIVE
2.After the installation is complete, set the tool installation path in your $PATH as below:
set path= $<MMSIM_INSTALLATION_PATH>/bin/:$<INCISIVE_INSTALLATION_PATH>/tools/bin:
$<IC_INSTALLATION_PATH>/tools/bin:$path

I have several doubts related to this error:

1) How can I check out where MMSIM and INCISIVE are installed?

2) Where do I have to write this thing of "set path=$<MMSIM..."?

I've searching on Internet about how to solve this issue. People say that there's a file ".cshrc" where the variables are defined, but instead I have found a ".profile" where the license is defined... I don't find any example of typical file ".cshrc" or ".profile".

I would appreciate so so much an answer that could help me to solve this error and begin to simulate circuits. I apologize because I have no idea about unix, and unix variables.

Thank you so much,

Irene

Hi,

I would like to launch my simulation on a Remote machine.. I would like to know the procedure and the settings required to launch simulation on remote host in ADE-L and ADE-XL.

Thankyou.

Hi all,

I have to do noise simulation of DAC+VCO. So I am doing Pss-Pnoise simulation. For DAC, there is witch capacitor circuit, and input of the DAC are clock signal and trim bit (according to which DAC output voltage get set). According to the DAC output voltage VCO gives a output frequency. I am confused how to do the noise simulation of this schematic and what should be the setting in the Pss-Pnoise simulation. Any lead will be appreciated. Thanks in advance.

Is there a particular syntax which can be used for the probe= part of a ccvs instantiation in spectre that would let me refer to something one hierarchy level up?

What I am looking to be able to do is create a cell that has a CDF parameter named probe.  I want to instantiate this cell (call it "mycell") into a higher level cell (call it "mytop").  Then I want to have one or more ccvs inside of mycell that can use voltage sources or iprobes in mytop as the probe instance.

The spectre netlist would then look something like:

subckt mycell(out, gnd)

parameters probe

H1 (out, gnd) ccvs type=ccvs probe=../probe

subckt mytop()

myv1 (sig1, gnd) vsource type=pulse .....

myp1 (pr1, gnd) mycell probe=myv1

ends mytop

Thanks

-Dan

Hi All

I have a rookie level question. I am trying to run a transient simulation and I need a "multi-tones sine input". Like Vin=A1*sin(w1*t)+A2*sin(w2*t)+A3*sin(w3*t).

I find Vsin but that only have one tone. 

Can anyone tell me how to achieve a multi-tone sine signal?

Thanks

AllenD

Hi team

I have a quick question concerning variable design in cadence. I am an experienced ADS user but new to Cadence. I realized a major difference between ADS and Cadence concerning variable setup.

In ADS, the variables are built in with the circuit so if I design a localized circuit with variables (for example, a LNA, a mixer, a filter, with a few variables of the size of the transistors, cap value etc), I can just create a symbol of each of the localized cell and use it as a part of a bigger circuit directly (as for a whole receiver) and all the variables will not interfere with each other even though they have the same name.

But when I am trying to design in Cadence, the variables are built in with ADE simulation environment. Hence, when I did the same thing as I did with ADS:

1. design the localized cell of independently ( LNA, filter, mixer)

2.Incorporate the LNA etc. into the receiver. But when I launch ADE, all the variables popped up and non of them have any values.

Do I have to re-enter all the variable values?

Is there any way around it?

Thanks

Hello,

I am trying to create a near ideal voltage buffer using the components of analogLib. I have tried using vcvs and other controlled sources. All these perform the function correctly but always have sharp frequency spikes and dips in the input and output impedances. I can understand if the spikes are insignificant but some of these come to around 90% of the maximum impedance value so when placed in actual circuits it affects the performance at these frequency notches. I have tried using feedback Rs and Cs but they don't seem to help.

Attached below is one example of vcvs under 2port SP analysis where Z11 is shown.

The port settings are:

Port1: Resistance=50ohm; SourceType=Sine; PortNum=1

Port2: Resistance=50ohm; SourceType=DC; PortNum=2

Simulator: Spectre
SP Analysis: 10M 10GHz ; Single-Ended

Wondered if anyone could recommend a solution.

Thanks.

Chris

Hi,

I have IC6.1.5 with (I think) Incisive 12.1. I work with AMS 0.18um technology.

I want to implement a digital circuit which I would make using Virtuoso, implementing gates "by hand". However, I want to use the tool-chain that comes with Cadence (Incisive, Encounter RTL and Encounter Digital Implementation, if I am not wrong). The thing is I can't find any documentation nor iLS training course covering at least the use of Incisive.

Where can I find some information in this regard?

Thanks!

Hello,

I have a standard logic gate library that has all the different logic gates with ppar for passing the nmos and pmos (width, length, nf)  values to the symbol level (an inverter for example).

So when I have a simulation setup for a larger digital block (using function views), all these Design Variables (maybe 50 of them) will need to have a value (it doesn't really matter just can't be left empty) for the AMS simulator to run. 

Is there a way to import a file containing all the sizing information for the gates so I can run the simulation? 

Thanks in advance,

Kevin

I am using Innovus Implementation system V15.20 for my design flow, 

My design contains custom made cells for which lib and lef file has been generated manually (using liberate and abstarct tool respectively), 

During the backend flow, when I'm trying to insert core filler in the post routed design. I see that the core filler is not inserted below the vertical 

power stripes which is causing DRC violations in the design. 

Please help me fix this.

The picture of filler cell not inserted in the design is attached and the command used for filler cell insertion is : 

addFiller -cell feedth9 -prefix FILLER -doDRC
addFiller -cell feedth3 -prefix FILLER -doDRC
addFiller -cell feedth -prefix FILLER -doDRC

Thanks in advance.

I'm trying to design a 10MHz clock in virtuoso. But when I'm using ADE L for transient simulation, output graph do not show proper result depending on simulation time and this simulation time. for higher simulation time,  it provides different result. For example, this is the output graph for "transient 0 1.1u moderate" simulation of my circuit:

near end, output pulse swing between 1.6V to -1.7V (approximately) volt. So to see the output pulse better, I raise simulation time to 1.5u. Now, for " transient 0 1.5u moderate" simulation, output graph is:

not only output graph is distorted , look at the output magnitude , its within mV range. in 1u to 1.1u range, there is no pulse. Where did the pulse go ??  

Could you please, explain me why my simulator acting like this? I'm sure, it has no relation with my circuit as I'm simulating same circuit for different time range. Is there any kind of restriction or settings problem? 

thanks 

Hello everyone,

I am trying to plot Phase Margin versus a parameter that was swept using parametric analysis. I have tried to plot this using the direct plot but unfortunately it didn't plot what I wanted. Basically I want to check how the PM changes with respect to that parameter.

Does anyone has got an idea on how to do this please?

Best regards,

Ameli

Hi,

I am aware of starting multiple simulations in ADEXL (Options -> Jobsetup). However, I wanted to change some circuit variables and run multiple parallel tests, but not all permutations. For ex, if there are 3 variables, x , y and z with each being assigned to say 5 values, i would have 125 tests if i ran all of them, but i want only a subset of those. So I am setting x to say 3 values while y & z are a particular value etc. 

So this basically means, I will have to start a simulation 3 times. However, I cannot run the next one while one of them is completing. Is there a way to start multiple tests at the same time (without creating new testbenches?)

Hello,

I need to create a model of a current source in verilogA but the value of the current depends also on the process corner. Is there a way for the verilogA model to detect what corner the simulation runs with? In ADEL we specify the corners through an include statement like this:

include <model file> section=typical

Thanks