Actually what i want to do
I have two similar cells layout in which I have created many parameter (repetitions of contacts and vias, and stretch lines). In one cell I have set the no. of via and contact through parameter which I have created using pcell. I want to see that parameters on screen and set the others cells parameters.
So basically i need to see the properties of layout of two cells together. Could we do that? I am using virtuoso IC Version 6.1.5 for layout.
Dear Sirs.
I want to make my little Standart Cell library.
I want that in my library there must have been not only gates but also triggers.
How to choose the necessary and sufficient set of standard cells for a standart cell library?
By what principle is the selection of cells? (It is clear that there is a variation of _X1, _X2, ...)
How to determine the size of transistors in cells? Align the delay on the 0->1, 1->0 or the rise time, the fal time?
If possible, advise literature on this issue.
Thanks.
Hi,
It seems the ocean script generated from ADEXL is able to cover all functionalities from the GUI. However, there's one thing I have yet figured out and wonder if anyone can kindly offer some help.
If my simulation output expression is "vb_value", and swept variables are vdd (0.9V, 1V), corners (tt,ss,ff), temperature (0c, 100c), after ADEXL run, a tabulated vb_value results will be generated, with flexibility depending on "detail" or "detail-transpose", and the GUI allows to export the data to .csv file.
Now with ocean run, I wonder what will be the code to save the "vb_value" to a file, with format as below:
0.9V, tt, 0c 100mV
0.9V, tt, 100c 130mV
.........
1V, ff, 100c 150mV
thanks!
Kevin
Hi,
This might be a simple question for those who are skilled in spectre but it seems I can't figure out how to do the following. I want to run two transient simulation, the second one starting from a point in time where the first simulation finished or perhaps at a point of time somewhere during the run of the first simulation. Then I would like to stitch together the results of the first and second simulation. I hope this is possible and going from the first to the second simulation can be done quite seamlessly.
Thanks for your help.
Hi,
I'm simulating a test bench consisting of a crystal oscillator, followed by several inverter stages that act as buffers.
I want to simulate the phase noise at the output of the last buffer, and eventually see how the added buffers contribute to the total phase noise.
What is the most accurate analysis to do in this case? PSS+PNOISE(sources option) or PSS+PNOISE(timedomain option)?
I don't want to see the integrated jitter or the noise in V^^2/Hz, but the phase noise at the output of the last buffer.
Thanks
Hello,
I have a spectre model for a layout only component (no netlist) and I want to simulate it along with my rest of the circuit.
I followed the guidelines in "https://community.cadence.com/cadence_blogs_8/b/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade"
in which i created a symbol, copied the symbol view to spectre view and modified the cdf for the block/sub-circuit.
Now, when I instantiate the block in my testbench where it is connected to other blocks and components from analogLib, the simulation fails at the netlist level with the following error
Begin Incremental Netlisting Sep 5 15:39:23 2017
*Error* eval: unbound variable - simVerilogFlattenBuses
End netlisting Sep 5 15:39:23 2017
ERROR (OSSHNL-514): Netlist generation failed because of the errors reported above. The netlist might not have been generated at all, or the generated netlist could be corrupt. Fix the reported errors and regenerate the netlist.
...unsuccessful.
However, if i remove all the other components except the block from my testbench then simulation passes, ofcourse the simulation itself is meaningless but aleast it generates the netlist with my component displayed as below
I2 (net3 net2 net01) test_bp
Can someone shed some light on what I am doing wrong?
Thanks
BR
Hi,
i have setup a testbench that contains a vprbs source. When running a monte carlo analysis with e.g. 200 points only the first point differs from previous started runs.
All other points are equal (min=max=mean). When i remove the vprbs source the mc-analysis works as expected.
The source has not to be connected (in fact i do a dc analysis). When changing the sampling method to "Low-Discrepancy Sequence" insted of "Random" it starts working again.
Is there a way to use the Random sampling method in combination with a vprbs source?
Version: IC6.1.6-64b.500.13
Best regards
Mirco
Hi,
I would like to know if is possible to avoid compiling the Verilog/sytemVerilog views every time you generate an AMS netlist in ADE-L (based on a config file with a sytemVerilog template).
The compilation time is extremely long and I only want to confirm if there is no netlist errors (no simulating).
Thanks.
Hi,
I'm using Incisive 13.20 .
I'm having a strange case that for $cds_get_analog_value(hierachy,"flow") , the result is a delay value of previous time step.
For example:
Time = 1e-06; I = 10e-06; I_cgav = 5e-06
Time = 2e-06; I = 15e-06; I_cgav = 10e-06
And it only happens for current assertion, for voltage assertion cds_get_analog_value works fine.
Is it a bug only on Incisive 13 and is it already fixed for later version?
Hello,
I have this MDL file:
alias measurement mdltest {
run tran
print fmt("%g %g\n", xval(voutp), yval(voutp)) addto="sample.txt"
export real divided = V(voutp) / V(voutn)
}
run mdltest
and I run it with this command:
spectre =mdl main.mdl input.scs
During the simulation, a sample.txt file is created and the X and Y values of the signal are periodically written to it, as expected (it is important that I do not have to wait for the simulation to end).
I would expect the wave file, called mdltest.meas_tran (in this context), to contain a signal called "divided" and this signal should be the ratio of voutp and voutn at every time step of this transient simulation.
Instead, I have a signal which has only a single point of data. Why is this happening? The reference manual is not very clear on how to generate and plot a new signal from an expression.
Thank you and best regards,
Patrik
Hello,
I've been using verilog-A to model devices for quite sometime and I wanted to ask what differences are there between the user define model (written in verilogA) and a built-in mosfet model, for example, from the simulator's perspective.
For example, I have a kit with its specific devices and their models are written in .scs file. Those files simply include the parameters passed to the model equations, I assume, that are hard coded in the simulator. On the other hand, when I write the verilogA code I define both the equations and the model parameters.
Does the simulator interpret both models the same way in terms of the numerical algorithms used (Newton-Raphson, ..etc)?
Does the simulator process the verilogA equations directly or there is some intermediate step to translate the verilogA code to another form then start solving the equations? (something like a synthesizer in digital). The reason why I am asking this question is that I read some articles about verilogA and they recommended not to overuse the verilogA functions such as ddt , for instance, to ensure proper convergence. So, it sounds to me like there is some intermediate interpretation step done by the simulator before solving the equations.
Thanks
Hello,
I want to create some layout only custom IP blocks(inductors/balun etc.,). I can draw their layout and modify them according to EM simulation results. During the modification time, I am simulating them in cadence using S parameter blocks. Once I am satisfied with the performance, I am making a simple spectre model out of it. So in the end, I have the following views for my custom block, layout, symbol and a text file defining the model.
Now, what I want to do is use my custom inductor in my design. When I draw a schematic, I instantiate the custom inductor there along with other components and make a cell out of it. Now, my question is how do I simulate my newly made cell which includes the custom inductor? Basically I have to somehow tell virtuoso how to netlist my custom block and which model to pick for my custom block.
I did post earlier a part of the problem here "https://community.cadence.com/cadence_technology_forums/f/38/t/37704"
In this post, I am providing more context to what exactly I am doing and looking for suggestions which either can help me solve the earlier mentioned problem or can recommend me a workflow (schematic entry,lvs,pex), where I can use custom blocks.
BR
Hi,
I'm new to OCEAN/MDL..
I need to print all the voltages and currents in the circuit for further text processing. I don't know the nodes and terminals beforehand.
SPICE syntax .print v(*) i(*) works fine but I want to format the output as below.
Node1 voltage1
Node2 voltage2
Term1 current1
Term2 current2
1. Is there any way to format the .print statement in SPICE syntax?
2. Which is the right tool to do this task? OCEAN or MDL or SPICE or any other ?
Thanks
Ramakrishnan
Hello,
I've recently installed the Cadence software in my institution's computer, I'm running IC6.1.7 on a CentOS 7. When I tried using the Assura package (ASSURA41) for a DRC run , it failed. The Log ends with this message:
Running in restart mode.
*WARNING* m2connect fd 6, 1 tries, errno 113 No route to host
*WARNING* Failed to connect to frmpsd on mentorlabge2. Success.
*WARNING* Failed to append to the database.
***** aveng terminated abnormally *****
***** aveng fork terminated abnormally *****
*WARNING* aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated
Perhaps I should note that "mentorlabge2" is the Computer's name. I'm using the PVS license to run Assura.
I've looked in several different forum posts and also in the documentation on the support website but couldn't find a similar problem...
I'm not sure what the error means so I don't even know how to begin troubleshooting this...
The full Log message is attached below.
(Please visit the site to view this file)
Thanks in advance!
Gabriel Fanelli
The system admin at my university informed me that ASSURA has been replaced with the Physical Verification Package this year. I had some questions which I was hoping someone from Cadence support could answer.
- The foundry DRC deck files I am using Cadence Proprietary ASSURA deck and Skill formats and are meant for use only with ASSURA. Is there any way to makes these files work with PVS going forward?
-Also are there any RAKs detailing the use of ASSURA and PVS in an Analog-Mixed Signal design flow from Cadence support?
Dear all,
I am creating some expressions on ADE-XL (under Outputs setup) and I am having problems to do a simple phase margin calculation, since sometimes the phase starts at 180 deg and other times -180 deg or 0 deg. How can I get around this, once the usual functions from the calculator don't solve this problem ?
A ternary operator would work for this case, but I don't think it is possible to implement it in these expressions.
Best regards,
Pedro
Hi,
I'm simulating a 80MHz crystal oscillator, so it is a circuit with an high Q (around 80k).
I want to run a transient simulation of this circuit, and I'm experiencing that the results are a lot dependent of the step and maxstep of the transient simulation. As regards the accuracy, I set it to "moderate".
I want to simulate the start-up time of the XO: if I set the step to 1n and maxstep to 2n, I simulate a start-up time of around 400us, if I use 10ns of step, I find around 1ms of start-up.
So I'm wondering what is the best setup in this case, what values to chose for step and maxstep and if moderate as accuracy is ok
Thanks
Hi,
I'm simulating a test bench consisting of a crystal oscillator, followed by several inverter stages that act as buffers.
I want to simulate the phase noise at the output of the last buffer, and eventually see how the added buffers contribute to the total phase noise.
I'm using PSS+PNOISE(sources option). The PSS uses the Twotier Method and the oinnode+ is on the crystal pin (not at the output of the last buffer). In the PNOISE instead, since I want to calculate the PN at the output of the last buffer, I used as output (Positive Output Node) the output from the last buffer
Is this setting correct?
Moreover....
Since the output is a squared waveform(due to the buffers) I'm selecting an oversample factor of 8 and an high number of harmonics. However, PN results increases when increases the number of harmonics.
Why this? Is an higher number of harmonics more accurate?
Note that from 40 harmonics on, the PSS fails to converge.
Thanks
Giuseppe
Hello,
I'm working on cadence virtuso Layout L or XL
Cadence version ==> cadence/ic/06.16.050
Calibre version ==> mentor/calibre/2017.1_25.22
I do only layout, I' drawing only elementary structure such as MOS or CAPA so on then these structure wiil be electrically characterized. Therefor, you can understand, I don't do schematic.
I did any check on my layout as Design Rules Check (here all is perfect).
Then we are using Layout versus Schematic to check a short/node between different layer ( Ex : Metal1 (layer) pintext (purpose) and Metal2 (layer) pintext(purpose)), let's have few minutes to details this operation.
We assume that a semiconductor wafer includes a plurality of chip areas having circuit elements, a scribe line area for defining the chip areas, and a plurality of test element group (TEG) modules
The TEG modules are group formed on the scribe line area. Each of the TEG modules has test transistors, a common source pad, and a common body pad.
A global gate pad is commonly connected to gates of test transistors in the test element group modules.
Global drain pads are shared by respective test transistors in the TEG modules.
So to check the right connection between my PADS and the Gates, Source and drain (i.e physic connection for example metal connection), on one side we put the label (label = pintext) on the gate and on the other side we put a label on the pad, we repeat this operation for the source and the drain.
We are using LVS tools to retrieve a report about connection, we check the report to see whether label gate is connected with label Pad or not in other words we check if there is a short.
Now my issue with this method, I can't be able to detect a "right short" from "wrong short" , sometimes I layout complex structure with lot of connection and in my lvs.report several node results are shaked in one paragraph/section, this makes the analysis difficult.
Hereinafter an example of LVS with "right short" ( no complex structure ;) ):
Here in my extraction results I can see that my diode is connected with the PAD1 and the bulk is connected with the PAD2.
Hereinafter an example of LVS with "right and wrong short" ( no complex structure ;) ):
Here in my extraction results I can see that my diode is connected with the PAD1 and PAD2 and the bulk is connected with the PAD1 and PAD2.
In this case it's easy to detect the problem but when the structure is more complexe it's very complicated...
We know that LVS tools is not suited for this task and I 'm working on another method more safety but maybe you know a better solution ?
Thank you.
Hi all,
I am relatively new to the Encounter tool. I am using Encounter v6.2 to place a simple design.