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expression syntax for schPatchExpr

August 2, 2017, 9:34 pm
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I am designing a circuit, where I need to connect a 32 bit wide bus to another bus which is 32 bits wide. I am trying to use a patch with the appropriate schPatchExpr, but I am not able to get the syntax right.

I tried the following

and get the following error

Error: Patch cord "I20" -270004): Illegal name syntax - Syntax error in connection expression.

If I try creating the patch with the following expression in schPatchExpr

I get the error

Error: (SCH-3489): Shorted terminals - memTerms'address_lrc_ram<31>' & 'address_i<31>' thru signals 'address_lrc_ram<31>' & 'address_i<31>'

Could somebody help me with the syntax for the schPatchExpr so that I am able to connect all 32 bits of the bus correctly.

Thanks

Prashant

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Spectre VS Hspice in simulation speed- questions and concerns.

August 7, 2017, 1:24 pm
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Hello,

In my simulation by using Cadence Spectre running in the command line mode (e.g., call runSimulation with input.scs and extract performance using ocean script), the time analysis is as follows.

For example, one simulation time by using the Spectre simulator is TSim = 4.45s and the time spent in licensing is 3.66s which is 82.3% of TSim. The time for running the SKILL-language-based Ocean script for extracting performance is TOcnExt = 5.5s, and I am not sure if the licensing check is involved in the ocean script execution or not. So, for simulating one netlist and extracting the performance will take TSim + TOcnExt= 9.95s. While in the work:

  R. Castro-Lopez, O. Guerra, E. Roca, F. Fernandez, An integrated layout-synthesis approach for analog ICs, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27 (7) (2008), 1179 - 1189.

the simulation was run by Hspice (say HspiceD) and was performed on a PentiumIV at 1.3-Hz PC in 2008. Their reported CPU times was 612.31 seconds for 2437 iterations.

So in average, 0.25s/iteration. Such a huge difference. I assume the data from an IEEE transaction level paper is trustable.

If the accuracy of simulation results only rely on the device model included, no simulator is more superior than another. (Maybe Spectre has a more fancy and powerful IDE.) Then why not always using Hspice due to its dominant position in run speed.

Anybody has a knowledge on this? 

Kind regards,

Alex

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NF of Demodulator

August 9, 2017, 10:33 pm
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hi

As the input and output frequency of the demodulator is different, i want to learn how to get the NF for a simple demodualtor specially using Cadence. If you have any good reference kindly share. Thanks

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iterated instance with different views to use, hierarchy configuration

August 10, 2017, 1:58 am
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hi all,

I have an iterated instance e.g. ADC<0:9>. I am trying to switch views in the hierarchy editor such that ADC<0> is set to e.g. 'schematic' view and ADC<1:9> are set to e.g 'behavioral' view.

I have tried to browse the tree view in the hierarchy editor, but the iterated instances are listed on a single line, and such can only select 1 'view to use' for all iterated instances.

Is there a way to do such a hierarchy configuration?

Thanks for your help. Best Regards

Dani

-- cadence virtuoso IC6.1.7

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DRC check in Integrated PVS environment

August 10, 2017, 11:55 pm
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Hi,

I want to check my DRC errors with the Integrated PVS environment. 

How can I actually see where all of my DRC errors are? I can only see instant DRC errors as I draw (e.g. M1 spacing minimum). In other words, I would like to active the PVS Results Manager Brower so I can see an overview of what DRC errors I still need to fix. 

This is first time trying the license so it can be we don't have everything installed correctly.

Thanks

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guide needed for simulating the circuit with script

August 11, 2017, 5:36 am
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hello, guys,

    I used to simulate the analog circuit by clicking the GUI provided by IC616 and mmsim14.  I find it's such a burden to simulate the same circuit for so many times. for example, if I design a specified OTA including only 9 mosfets and 2 capacitors. I have to adjust the dimensions for uncountable times to find  good ones, especial for a optimal one(e.g noise optimation).  

Now I want to do this in an automated way. I want to write the scripts in order to let the program calculating the proper bias voltage and mosfet and passive elements dimensions for me with the optimization method I give. Here is problem: where can I find the materials that could guide me to learn the scripts language(I know there is pspice)?  I hope this language could allow me to call the simulator(like mmsim14) to do the needed simulation such as DC AC STB PSS etc.... and return the simulated results to the specified directories. and then I could transfer these results to the python scripts that I write to find the optimal values. Or a better situation is I could use the functions provided by the IC616 Platform(I believe it's exist in the waveform tools, but how do I call these functions?) instead of using the python scripts.  For a single simulation, maybe the result is not the optimal one, so I need to call the simulator to do the former simulation again if the current values don't meet my targets values until I find the optimal one( the ones that meet my targets values). 

I have the systemic design methodology. Could anyone give me some links(including the RAK or documents) or the name of the pdfs in the IC616 doc files which could guide me to learn the appropriate language to describe the detailed circuits and call the ADE simulator and do the Loop to find the target values?

 

thans in advance!

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SKILL command to turn off grid track

August 11, 2017, 10:06 am
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Hi,

I have two SKILL code related questions in virtuoso:

In layout, what is the command that controls ON/OFF of Palette/Grids/Tracks and Palette/Grids/Grids, I tried to guess based on command list from Options/Bindkey editor/Layout, but could find corresponding ones. 

In Viva waveform viewer, what I had to do almost every time is:

- Graph Properties/General/Color/Background: change to white

- Axis Properties/General/Font/Color: Font Style change to Bold; Size change to 12

- Trace Properties/Type/Style: change to Medium

It'll be very helpful if we can figure out command for those, so that they can be set as default in .env file I guess.

Thanks,

Kevin

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voltus-fi with tsmc qrcTechFile

August 12, 2017, 5:13 pm
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Hi

I have a question on voltus-fi with tsmc qrcTechFile.  I am using the following version:

Voltus-Fi version being used is as follows:
******************************************************************
 Voltus-Fi batch mode application (64-bit) - High Capacity Power IR/EM - v06.17-e215_1 ((08/22/2016 17:32:20))

When I use the tsmc reference flow qrcTechFile, I got em and ir reported generated properly.  But when I use the pdk qrcTechFile, no em ir report is generated and there is just this warning message from the log file.

Warning from spectre during transient analysis `tran', during Reliability Analysis `rel'.
    WARNING (EMIR-2603): Failed to run command line: '/server/cad/tools/cadence/SPECTRE161/bin/emirreport -64 -c /server/home/rtang/simulation/rt_scratch3/tb_inv/maestro_she_bad/results/maestro/ExplorerRun.0/2/rt_scratch3:tb_inv:1/netlist/emir.conf -db /server/home/rtang/simulation/rt_scratch3/tb_inv/maestro_she_bad/results/maestro/ExplorerRun.0/2/rt_scratch3:tb_inv:1/netlist/../psf/input.emir0_bin -outdir /server/home/rtang/simulation/rt_scratch3/tb_inv/maestro_she_bad/results/maestro/ExplorerRun.0/2/rt_scratch3:tb_inv:1/netlist/../psf/'. Can not generate EMIR report with emirreport.

I ran the Techgen -tech_version and noticed the 2 qrcTechFile's version are different:

Techgen -tech_version qrcTechFile_pdk


 CADENCE TECHFILE FORMAT  (RC) (BASE) 16.1.1-s134 2017/3/14,19:8:44/14,19:8:44

Techgen -tech_version qrcTechFile_reflow


 CADENCE TECHFILE FORMAT  (RC) (BASE) 15.2.4-s462 2016/8/25,4:47:11/25,4:47:11

I wonder if the reason I am not getting a report from pdk qrcTechFile is due to voltus fi version not compatible?

Thanks,

Ray

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VerilogA issues -- transition function

August 14, 2017, 9:23 am
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Hello,

I'm creating a verilogA model for a circuit component and wish to have smoothly transitioning variables. The variables are of the real data type and I can't seem to use the transition function on them without the simulation returning an error. Is there some equivalent of the transition function that I can use on real data types just like I can use for currents (e.g.). Above I have pictures showing the variables that I wish to smooth out. I'm trying to eliminate the flat plateaus where the variables are constant.

Thank you

Paul

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Cadence Virtuoso Default Libraries

August 18, 2017, 7:48 am
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Hi

I am very new to the cadence tools. I would like to know what are the default libraries the cadence provides in the virtuoso environment such as analoglib, basic etc. I think the list may me many. But I very much interested to know the libraries which provides working schematics for digital devices such as counters, decoders, multiplexers, op amp, switch, comparator, ADC, DAC etc. Or do we have any example schematics provided by cadence. This will help me to know whether I can reuse the existing examples or build from scratch

Please guide me.

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Need to Set Design before issuing this command

August 20, 2017, 5:10 am
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Hello,

I am using ADE L in Virtuoso version IC6.1.6.500.1
All of a sudden I try to use my saved spectre_state for a schematic and it shows me " Need to Set Design before issuing this command" . I dont know how to solve this, so I could not perform the simulation. Can you please help me understand this issue!

Thaanks

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VerilogA Error running Spectre

August 23, 2017, 4:13 pm
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Hello all,

I have a veriloga module (just a regulator) in my schematic and when I try to simulation the schematic ADE L Spectre I am getting the following errors in spectre.out

Created directory input.ahdlSimDB/ (775)
Created directory input.ahdlSimDB//5496987385e7949d572f19a4275e89ce.Current_Limiting_Regulator.ahdlcmi/ (775)
Created directory input.ahdlSimDB//5496987385e7949d572f19a4275e89ce.Current_Limiting_Regulator.ahdlcmi/Linux/ (775)
Compiling ahdlcmi module library.

Warning from spectre during AHDL read-in.
WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.
ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//5496987385e7949d572f19a4275e89ce.Current_Limiting_Regulator.ahdlcmi/Linux//..//ahdlcmi.out for details. Contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
ERROR (SFE-91): Error when elaborating the instance Current_Limiting_Regulator. Simulation should be terminated.

I read some questions here before stating the problem may be running 32 bit os, but the linux machine and PC are both 64 bits. 

Any insight to this will be helpful.

Thank you,

Kevin

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Parasitic extraction for interconnects

August 23, 2017, 5:27 pm
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Hello all,

I need to run Calibre parasitic extraction (PEX) for some interconnects which are basically a combination of metal layers and vias. So no schematic corresponds to that, and I just have a layout consisting of metal layers. That is why LVS can not be run for that, and no PEX result can be obtained. I realized that we may be able to use some dummy resistors in the schematic (in the PDK that I use, I think they are called "lvsres") to create a dummy schematic. But "lvsres" has no layout in the technology library, it's just a symbol, so again no LVS can be run I assume. Does anyone know how to work with "lvsres", or how to run PEX for a cell with no schematic?

Thank you

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Verilog-A model equivalent to primitive model?

August 23, 2017, 6:21 pm
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Hi,

I'm build a AMS test bench (ADE based) and try to replace all resistor/inductor/capacitor from analogLib primitives to Verilog-AMS models.

The purpose is to make every elements flexible to be changed in the AMS stimulus sequence by OOMR without too many ADE variables.

An example of inductor is as below (similar for resistor and capacitor), my question is this model ( I and V linked by ddt() or idt()) accuracy is the same as Spectre primitives in AMS simulation?

If not, how can I improve the accuracy to make sure my simulation results will be the exactly the same as those components in Spectre primitives?

`include "constants.vams"
`include "disciplines.vams"


module ams_inductor(MINUS, PLUS);

inout MINUS;
inout PLUS;

electrical MINUS;
electrical PLUS;

// Default DC inductance
parameter real inductance = 1e-9;
parameter real tt = 10e-6;

// Variables for OOMR
real indSet = inductance;
real ttSet = tt;

analog begin
V(PLUS, MINUS) <+ indSet*ddt(I(PLUS, MINUS));
end


endmodule

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gmoverid in dc operating point is not equal to gm/id

August 24, 2017, 12:20 am
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Hi,

I just want to do the gm/id plot, by following circuit

.

and i included one scs file with "save NM0:all", i can got gm, id and gmoverid by dc simulation. use following 3 expression to get the gm/id plot.

found in weak inversion region,  why NM0:gmoverid is not same as getdata("NM0:gm"?result"dc") / getdata("NM0:id"?result"dc") ? thanks.

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layout-xl schematic numbering update

August 25, 2017, 11:26 am
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Hi,

I have a layout that is LVS clean with respect to its schematic but, since the last LVS check, all the instances in the schematic has been renumbered. How can I update a layout connectivity (I'm using ic6.7.13 and layout-xl, btw)?

thanks in advance.

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Exporting Horizontal Marker, selecting intercepts by zooming the graph doesn't work

August 26, 2017, 3:42 am
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Hello, I need to save the intercepts with an Horizontal Marker. I use Virtuoso IC6.1.7-64b.500.4 

I zoom-in the graph in Viva and I click on Marker -> Export -> Horizontal Marker. Unfortunately, the .csv file that I get contains ALL the intercepts between the ENTIRE waveform and the Horizontal marker, but I want ONLY the intercepts of the zoomed-in portion of the graph.

The same problem happens with the Horizontal Marker Table. In the manual  "Virtuoso Visualization and Analysis XL User Guide" (Product Version IC6.1.7 June 2016) is stated: "When you zoom-in a graph, the horizontal marker table lists only those intercepts that are visible in the zoomed-in portion of the graph.", but this does NOT happen to me, I see all the intercepts of the entire graph listed in the table, no matter how I zoom the graph. 

Is there maybe a setting to be changed? This problem didn't happen with Virtuoso IC6.1.6 that I was using last year.

I hope you can help me. Thanks! 

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missing instance in schematic

August 29, 2017, 3:55 pm
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Hi,

sometimes when I open a schematic, there are some instances missing, like instances from other libraries, that have been removed later on.

such instances will be displayed as a crossed box using those flashing lines, with text "missing instance" on it.

Can I hide the display of those missing instances so that the boxes are not visible in the schematic? 

Any suggestion?

Thanks!

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Pen Tool and node / point tutorial video

August 30, 2017, 7:19 am
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Hello,

I am super excited about the great features in Glyphs that Font Lab doesn't offer... much of your program is very intuitive but I'm having a hard time moving from my familiarity with Illustrator and Font Lab to your pen tool and how your points on a path work.I was looking for such Tool Overview Video that would explain all things in a proper way.
If someone could put together a short tutorial video explaining all the functionality of these features and some of the possible ways to use them that aren't as obvious or related to other popular designer software... i think it would be very helpful to your users and probably help your sales.

Any help is much appreciated!
Thank you.

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monteCarlo results in percent instead of absolute?

August 30, 2017, 12:39 pm
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Is there a simple way with monteCarlo sims in ADE-XL to show the min/max/std dev expressed as a percent of the mean?  For example, take a very simple case of a test bench which measures the resistance of a 10k resistor, instead of min/mean/man/std_dev being:

7k/10k/13k/1k

I'd like to see

-30%/nom/+30%/10%

Ideally this would be based off of a nominal run but I'm happy enough with using the sample mean as my reference point.  

I could do this as a real hack and have two instances of my DUT and compare one against the other (including the sqrt(2) factor) but that gives 2x the circuit to simulate.

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