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Well proximity parameters (scc,scb,scc) used in PLS simulation

July 4, 2017, 6:00 am
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HI,

Can anyone tell me how the well proximity parameters are used in model file (.scs)  while running PLS simulation?

My requirement is to find out how (WPE) well proximity parameters (scc,scb,scc) effects the threshold voltage of device. I have gone through the model file (.scs) already but I am not seeing any direct relation b/w the WPE parameters and threshold voltage. But in PLS simulation I can see that with WPE parameters variation my device resistance is getting varied. So I need to know how threshold voltage is modeled based sca,scb,scc parameters.

Regards

Anand

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Spectre: How to get rid of spectre.ic and spectre.fc?

July 8, 2017, 10:24 am
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Hi! I am running batch simulations over a large extracted design, so I need to trim down the size of the results directories to the bare minimum. The spectre.ic and spectre.fc occupy almost 50MB each, so I want to avoid generating them, but I haven't been able to figure out how...

-In my transient sim setup, tab "State file" I removed the text "spectre.ic"  and "spectre.fc" in the fields "write" and "writefinal", respectively, but the simulator seems to ignore this.

-In the "enviroment" options I have checked "Save state (ss)" and "Recover (rec)" to "n", but this also doesn't seem to have any effect.

Any ideas on how to achieve this? I'm using spectre version 15.1.0.679.isr14 64bit.

Thanks and regards,

Jorge.

P.S. I also noticed that even though I made sure to have no outputs selected for saving/plotting, and my "save all" setup is as in shown below, a "tran.tran.tran.dat" is still generated in the results directory. When I check its contents with the Results Browser tool, I see that one voltage node of my circuit is still being saved. Is this a bug, or spectre must by all means save at least one circuit node?

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transistor voltages (65nm / 28nm)

July 10, 2017, 2:20 am
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hi 

the transistor model in 65n has voltages range near 1.2 v (single transistor). What are the voltages in 28nm. (it also has super low voltage transistor). i am new in ic design so apologize for any non sense ques.

thanks

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Making a Summary Measurement in ADEXL

July 11, 2017, 7:29 am
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In the ADEXL Outputs Setup, is there a way to add a compound measurement that gets data over all corners run.

In my case, I want all edges of a certain measurement to switch within a certain time window.  I don't care about the absolute switch time, I just want to make sure that over corners they all switch within a certain amount of time.  I imagined doing this by being able to access the min arrival time over corners and the max arrival time over corners and subtracting the values and have that compared to a predefined specification.

Thanks

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Is there any way to convert .tf file into .tch file?

July 11, 2017, 2:19 pm
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I need *.tch file for creating RC corner in tsmc180 technology file. But they provide me with .tf file ? 
Is there any way to convert it ? 
If not, what format of file I should search for which could be used instead of *.tch file.

FYI: I tried to use .tf file instead of .tch file which is causing error. So I'm guessing  wrong format is the reason behind this. 

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RMS and AVERAGE Calculation with respect to power.

July 11, 2017, 11:05 pm
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I have designed a custom 5 bit counter. The "Pulse" Inputs are applied to the counter so that all possible input combination are applied to the counter (from 00000 to 11111). The output of counter is connect to a 5 bit DAC(ideal) written in verilog-a. I want to measure the dynamic power consumption of the counter. A transient simulation is setup for 30 cycles of output waveform. I have plotted the supply current through the counter. I have the folllowing two questions:-

1. Average Power:  To calculate power i took average of the supply current waveform of counter and multiplied it with the supply voltage.

2. RMS Power: To calculate power i took rms of the supply current waveform of counter and multiplied it with the supply voltage.

Which of the two powers represent the dynamic power consumption? I doubt whether one of them really represents dynamic power as the power does not increase with the frequency. For Example, the power for 1kHz is say 22uW then for 2k is 11uW and for 3k it comes out to be 15 uW.

Thank You.

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How to differentiate trace name using "Plot signals from all the open DBs" in ViVA XL browser mode?

July 12, 2017, 2:34 pm
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Hi,

I'm using ViVA XL 6.1.7. When I use "Plot signals from all the open DBs" feature for comparing signal, it doesn't show the trace result dir at trance name.

So, it is difficult to differentiate the traces. Only way is to open "Trace info" window and check one by one.

Is there any way to show result dir or result name with trace both together?

Thanks

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Title Block Properties Moving

July 13, 2017, 2:37 pm
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Hello,

I've created custom title blocks with custom properties. I have selected the justification, font, size, etc. for where they are located on the title block, and have placed them appropriately. These title blocks are in their own library, saved with unique names.

I place the title blocks, and populate them with the Edit>Browse>Title Blocks/Edit>Properties, or by double-clicking the default value on the page in question.

The properties move around without any perceivable pattern. They will hang off the edge of the page, move around inside or outside the title block, put themselves on top of each other, etc. I have to manually drag them back ON EACH PAGE, ONE AT A TIME to where they belong when I generate PDFs, then they will move again after anything changes (save/open close/update/change properties/change sheet size etc.).

I have tried replacing/updating the title blocks/cache both preserving or replacing the part properties. I've tried combinations of deleting them/clearing design cache/saving title blocks differently, etc. No luck.

What am I missing? 

Thanks

AJ

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Usage of variables belonged to different measurement functions in spectremdl

July 14, 2017, 3:54 am
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Hi,

I am using spectremdl for measuring the performance of my analog circuits. During simulation, one variable is generated using the DC run and the other using transient run. I need to calculate a final variable using both these variables. Since they belong to different alias measurement block. The script is throwing error. Could you please suggest me a solution?

Example

alias measurement dcrun {

export real V_a

}

alias measurement acrun {

export real V_b

}

I want the following
export real V= V_a - V_b

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.lib files generation for custom analog design

July 18, 2017, 2:48 pm
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Hello,

I wish to generate .lib files from a cadence library analog cell, Is there a direct way to generate that from ADE GXL testbench ? 

I read in this forum about DCM but couldn't find it in GXL ?

Thank you,

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.cdsplotinit and trying to print schematics on 11x17 paper

July 19, 2017, 5:28 pm
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Hi,

We recently installed new printers which have the option of printing to standard Letter size (Drawer 1) or 11x17 (drawer 2).  I added the printer to my .cdsplotinit file however, every time I select 11x17 in the plot options, it still prints to Letter size.  Here is what I have in my .cdsplotinit:

Secure_Print|Canon iR-ADV C5250/5255 PPD: \
     :manufacturer=Canon: \
     :type=postscript2: \
     :spool="lp -onobanner -o sides=one-sided -dSecure_Print": \
     :query=lpstat -oSecure_Print: \
     :remove=cancel $1 Secure_Print: \
     :resolution#1016: \
     :maximumPages#10: \
     :residentFonts: \
     :PPDFile=/etc/cups/ppd/Secure_Print.ppd: \
     :paperSize="Letter" 612 792: \
     :paperSize="11x17" 792 1224:

What more do I need to add to get it to print to the correct paper size?

Thanks

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vbit source in analogLib

July 19, 2017, 7:44 pm
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I tried using the vbit source from analogLib in cadence virtuoso 5.1.0 04/26/2009. I would like to simulate my design  with a specific bit pattern. but it gives me error. please see attached snapshot for the error .

 


 

 

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Basics about wire labels and general text

July 20, 2017, 12:17 am
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hi 

1) Can a wire be defined with two wire names with some dummy element between them. (actually during my simulation tests i have to bypass the switch to check the o/p therefore one name either at input or output need to be deleted.)

2) how can i enter the text in cadence schematic window (for some reference to remember about schematic purpose). I found text written in some example schematics of cadence.

thanks 

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How to reduce time needed before transient simulation to be started in case of large circuit

July 23, 2017, 4:57 pm
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Hi,

I have to run transient simulation for a very large circuit. But every time, before starting transient simulation( simulation for different times), it is taking a significant amount of time to find DC solution. I have set up "Initial Condition Parameter" of transient simulation as follows:

ic: all, skipdc: no, readic: spectre.ic; also i tried, readic:spectre.fc. But both of them, don't help to reduce the simulation time for DC convergence. Can you please help me on this aspect? And another question: What's the difference between spectre.ic and spectre.fc files and which one should be appropriate for readic field?

Program: @(#)$CDS: virtuoso version 6.1.6-64b ,Sub version: sub-version IC6.1.6-64b.500.1

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Using AMS pads on Virtuoso Layout L

July 24, 2017, 9:14 am
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Hi,

I am trying to include AMS pads (process AMS C35B3C3) in my layout but I am getting the BAD_SUBSTR_SUBTAP_FLOAT_ERC error when running Assura DRC. Regarding the pins, I am using the PIN PAD layer and I am naming the power and ground pins "vdd3r!" and "gnd3r!", respectively.

Why am I getting this error?

Thanks in advanced!

Regards,

David.

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Problem of RC Extraction with GPDK45nm(gpdk045_V_3_5)

July 25, 2017, 10:28 am
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Hi

When I was running RCX extraction using ASSURA with gpdk045 model. Always I'm getting warnings and then failed to extract layout. From the log file, some libraries models are missing in gpdk45.

Please see below log file.

 

Thank you

 

  Assura (R) Physical Verification Version av4.1

 

Copyright (c) Cadence Design Systems. All rights reserved.

assura version av4.1

 

 

Loading tech rule set file : /root/gpdk045_v_3_5/assura/techRuleSets

Checking out 1 license for Assura_RCX

 

Starting /mnt/cadence/ASSURA41_USR3_HF1_615_lnx86/tools/assura/bin/rcxToDfII /root/gpdk045_v_3_5/rcx.SRAM_cell_layout.rsf -t -cdslib /root/gpdk045_v_3_5/cds.lib -libdefs /root/gpdk045_v_3_5/lib.defs

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.06s.

*WARNING* lib.defs files and the -libdefs option are no longer supported. The file '/root/gpdk045_v_3_5/lib.defs' will be ignored. The cds.lib file '/root/gpdk045_v_3_5/cds.lib' takes precedence.

@(#)$CDS: rcxToDfII version av4.1:Production:dfII6.1.5:IC6.1.5.500.15 02/20/2013 00:18 (sfrh54) $

sub-version 4.1_USR3_HF1, integ signature 2013-02-19-2240

 

run on localhost.localdomain from /mnt/cadence/ASSURA41_USR3_HF1_615_lnx86/tools.lnx86/assura/bin/32bit/rcxToDfII on Tue Jul 25 21:48:38 2017

 

 

Loading tech rule set file : /root/gpdk045_v_3_5/assura/techRuleSets

Loading gpdk045/libInit.il ...

     Loading gpdk045/loadCxt.ile ... done!

     Loading context 'gpdk045' from library 'gpdk045' ... done!

     Loading context 'pdkUtils' from library 'gpdk045' ... done!

     Loading gpdk045/gpdk045_customFilter.il ... done!

     Loading gpdk045/libInitCustomExit.il ...

     Loading Environment Settings ...

     Loading gpdk045/gpdk045_PDKRegistrations.il ... done!

 

  *************************************************************          

  *              Cadence Design Systems, Inc.                 *          

  *                                                           *          

  *                    Generic 45nm PDK                       *          

  *                        (gpdk045)                          *          

  *                                                           *          

  *************************************************************          

    

 

     VERSION: 3.5

 

done!

Loaded gpdk045/libInit.il successfully!

*WARNING* No library model for device "g45inda".

*WARNING* (DB-270211): dbOpenCellViewByType: Failed to open cellview (g45cmim ivpcell) from lib (gpdk045) in 'r' mode because cellview does not exist, or cellview type is not recognized by dbOpenCellViewByType.

*WARNING* No library model for device "g45cmim ivpcell gpdk045".

*WARNING* No library model for device "g45inds".

 

Finished /mnt/cadence/ASSURA41_USR3_HF1_615_lnx86/tools/assura/bin/rcxToDfII

 

Starting /mnt/cadence/ASSURA41_USR3_HF1_615_lnx86/tools/assura/bin/avRCXxref /root/gpdk045_v_3_5/rcx.SRAM_cell_layout.rsf

@(#)$CDS: avRCXxref version av4.1:Production:dfII6.1.5:IC6.1.5.500.15 02/20/2013 00:13 (sfrh54) $

sub-version 4.1_USR3_HF1, integ signature 2013-02-19-2240

run on localhost.localdomain at Tue Jul 25 21:48:39 2017

Reading rsf

 

Finished /mnt/cadence/ASSURA41_USR3_HF1_615_lnx86/tools/assura/bin/avRCXxref

Constructing the RCX run script

*WARNING* at "RCXspice": ?extractMosDiffusionAP option will be retired in the next release.

 

Could not open file /root/gpdk045_v_3_5/assura/../qrc/RCXspiceINIT for reading

*WARNING* Bad return status from RCX script generator. 0x100

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APS simulation: When a DC supply isn't DC

July 25, 2017, 12:37 pm
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I'm getting strange behavior from an APS run and I'm hoping I can get some suggestions to debug/resolve the issue.  Basically, my waveforms are skipping around.  The problems started when I added a full extractions of one of the child blocks (other blocks were already post-layout).  The most egregious failure I've seen is the VDD supply.  For a single time step around 50ps into the simulation it drops down to 0 and then bounces right back.  This is a DC supply.  I'm seeing similar behavior on other pulse supplies where the voltage isn't following a straight line from start to finish.

I would suspect there was some convergence issue but the log file doesn't have any errors/warning during the run.  I've tried adding source resistance to the supplies which in the past has helped with convergence but it made no difference.

Any thoughts on how to debug this?  Options to try?  Ideas why a DC supply isn't DC?

Thanks in advance....

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scs file calls a verilogA

July 25, 2017, 2:48 pm
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Hello, 

I have a ".scs" file that calls a verilogA model. the line in the .scs file that does this reads the following:

memr_TMO_test p n memr_TMO_test HRS=HRS1 LRS=LRS1 Vtp=VtP Vtn=VtN

the verilogA model is called: memr_TMO_test.va 

when I run the simulation in ADE, I get the following error:

/research/seneca/freepdk/memr_TMO_test.scs" 16: Instance `memr_TMO_test' in subckt `memr_TMO_test' recursively calls subckt `memr_TMO_test'. `memr_TMO_test' should be updated to remove the call to `memr_TMO_test'.

can someone help with that

thanks

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Align Figure groups together

July 26, 2017, 3:10 am
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I'm trying to organise my schematic into various groups based on their function.

I can align the instances in each group but can't align different groups together, is this possible using the align tool?

Seeing as each group has a bBox property, I assume it can be done.

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Syntax for device check violation file assert statement

July 27, 2017, 7:20 pm
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Hello,

I would like to ask how to write device check violation files (for example devcheck.scs) I can include in my model files and use to check for violations.

I believe the correct syntax for example for a vgs voltage check would be:

nmos_name assert mod=nmos_model_name expr="v(g)-v(s)" max =[max_voltage] duration=[duration of violation]

Let's say I want to modify the above assert statement so it checks only when another condition is true: I want to check vgs voltage only when vgd>0 for example

or when ids >0.  How would I write that?

Thank you!

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