HI All,
Recently physical verification system tool is installed and integrated to virtuoso but the menu options are not working. when i am trying to use any option i am getting the following error
_pvsOpenIPVSrunform( 'erc ?timeout 30)'
_pvsOpenIPVSrunform( 'drc ?timeout 30)'
PVS Version: PVS 15.22-s262-64b
Virtuoso: IC6.1.7-64b.500.7
these are the versions of tools i am using. Can anyone tell me how to solve this?
Regards
Anand
Hi
I was using a laplace_nd function to realize a CTLE block as follows
V(vp) <+ laplace_nd((0.5*(V(INP)- V(INN)))*rl*gmn , hn , hd);
V(vn) <+ laplace_nd((0.5*(V(INN)- V(INP)))*rl*gmn , hn , hd);
whre hn, hd are declared as "real hn[0:2], hd[0:3];"
It worked well without any sort of convergence difficulties in bot AC and transient simulations. But since I wanted to change the values of hn and hd in between the transient simulation, I changed the laplace_nd function into equivalent differential equation as given below
V(vp) <+ ((0.5*gmn*rl*(hn[0]*V(vip)+hn[1]*V(vipd)+hn[2]*V(vipdd)))-hd[1]*V(vpd)-hd[2]*V(vpdd)-hd[3]*V(vpddd))*(1/hd[0]);
V(vn) <+ ((0.5*gmn*rl*(hn[0]*V(vin)+hn[1]*V(vind)+hn[2]*V(vindd)))-hd[1]*V(vnd)-hd[2]*V(vndd)-hd[3]*V(vnddd))*(1/hd[0]);
where
V(vip) <+ V(INP)- V(INN);
V(vin) <+ V(INN)- V(INP);
V(vipd) <+ ddt(V(vip));
V(vipdd) <+ ddt(V(vipd));
V(vind) <+ ddt(V(vin));
V(vindd) <+ ddt(V(vind));
V(vpd) <+ ddt(V(vp));
V(vpdd) <+ ddt(V(vpd));
V(vpddd) <+ ddt(V(vpdd));
V(vnd) <+ ddt(V(vn));
V(vndd) <+ ddt(V(vnd));
V(vnddd) <+ ddt(V(vndd));
The modified model showed exactly same AC response without any convergence difficulties. But it is showing convergence difficulties in transient simulations of same conditions (blowup parameter of nature Voltage was increased to accommodate high values coming to third derivative terms in the differential equation). How can I make the differential equation as convergable as the laplace_nd function.
Thanks and Regards
Quilon
Hi,
Is there any possibility that I can run $system() command in Verilog-A model. I want to an external script that computes some values and return it to my verilog-a parameter.
example:
S= $system("sh myfile.sh")
I check the documentation of virtuoso and Verilog-A but I couldn't found such command.
Any work around for it?
Regards
I am using cadence ic616 and calibre for lvs/DRC/xRC. I added a new layer in the kit (IBM 65nm 10LPe). I want that layer to be shorted during LVS. I learnt that CDS_thru can help with that and I have been trying to add several views of the CDS_thru to my device representing that new layer but still the LVS is not working. It is showing the following error:
No matching ".SUBCKT" statement for "memr_hfox" at line 62 in file "/home/samer1/cmos65nm/TS_Form_prog.src.net"
Source could not be read
can someone help with that?
thanks
Dear all,
I've been using ADE to run simulation for a long time. However, I found that when I have multiple ADE instances opened to run multiple simulations, for example, do some basic DC analysis on a small circuit, while waiting for a big long transient simulation to finish. When I open up the waveform viewer, cadence gets confused and it doesn't display the waveform properly, this gets even more annoying and frustrating when you have circuits nodes with the same name, and etc...
ADE XL does allow us to run multiple simulation at the same time, but we have prepared all the test setup before we hit the start button, which doesn't help my usage scenario. I wish to start another new simulation while the other simulation is already running.
I used to able to do that with HSPICE, where you have all your netlist, .log, waveform files in one folder. If you want to see the waveform, just open the waveform file with the viewer. However, with cadence, we have .dat file, whose file size indicates that this is the waveform file, but you can't open this up using the viewer (viva).
Please help us, other people in my lab seem to have the same issue.
Thank you very much,
Best Regards,
Menghan
Hello:
I am using Virtuoso Custom IC Design Environment Version IC6.1.7-64b.500.12
ADE L or XL ADE simulation setup toolbar is missing buttons. Mine just looks as follows:
How could I restore them to the default version.
The default simulation setup toolbar buttons should look like this.
I read in the ADE user manual but no luck.
Thanks a lot for your help.
Hello:
After updating to IC6.1.7-64b.500.12. I am having an issue where the PDK menu is not showing up in the command Interpreter Window. I didn’t have any problem with the previous version of IC6.1.7-64b.500.10.
Instead of the PDK menu showing in the CIW like this:
The menu disappears from the CIW like this:
The PDK menu must show in the CIW. That is the only way I am able to create a new library.
Thank you so much
Hello all,
I am having a problem where the number of ports on my SimCoupler module will not update within a Simulink schematic in matlab (.slx file). When I double click the module, change the number of ports and click ok the number of inputs and outputs remain at the default of 1.
As you can see in the picture below the number of inputs and outputs have been set to 2 but the schematic has not updated.
I am following the tutorial from "MATLABCosimulation.tar.gz" in the following directory ".../.../cadence_ic/6.1.6.500.13.2/tools/dfII/samples/tutorials/AMS" and this is where the SimCouplerLib.mdl file also comes from.
Matlab version is R2017a and cadence_ic is 6.1.6.500.13.2.
I have tried reverting to matlab version r14 as this is the one used in the tutorial but the same problem remains. I have also used the SimCoupler files from the following location instead : ".../.../cadence_ic/5.10.41.500.5.96/tools.lnx86/dfII/samples/AMS/Matlab" and again the same problem. There is no ".../.../samples/AMS/Matlab" folder within any cadence_ic version above 5.10.41.500.5.96.
Is there a more recent tutorial and SimCouplerLib.mdl available? Should I be using another version of matlab/Simulink?
Thank you in advance,
Oliver
Hi,
I want to export my digital design schematic in one process to another process in Cadence Virtuoso.
I export the schematic in verilog or EDIF.
When ı try to export and import the design in EDIF format the schematic is much more preserved. However I need to make changes in the EDIF file to make the import tool understand which is the equivalent cell in the final library. For example a D flip flop in the exported library will have a different equivalent in the imported library. Is there a quick way to make it automatic?
When I try to import the verilog export the schematic equivalent has different routing and symbol views and I cannot import some cells as they are because they lack of definition, they only have verilog file.
Could you please help me carry my design to another process library preserving the schematic view, symbols and connections?
Best,
HIDIR
I have started installscape.04.23 in CentOS -7 and when trying to install Cadence tools through DVD got from Cadence, it says
Location:
/run/media/usr1/1908_11042016/IC616_PART-1
Does not seem to be a good Cadence installation directory
Although through internet its working fine but it takes too much time.
Please suggest some reliable solution for installation.
Hello,
I am designing an instrumentation amplifier using the current balancing amplifier architecture. The differential voltage at the input is copied to the sources of the input pair and generates a current through the resistor R1.
I am running a noise simulation to obtain the output noise at the terminals of R1 which, for the specific circuit, is approximately equal to the input-referred noise. However, the resulting noise generated by the resistor R1 is much smaller than the predicted 4kTR by several orders of magnitude. On the contrary, it appears to be proportional to 1/R1.
I am not sure I can understand how increasing the value of a resistor reduces the noise generated at its terminals...
Hello,
I am confused about the concept of the stop view. Let's say I have a a two terminal device "X" that I implemented in verilogA and have some parameter in it. Once I save it as a symbol, those parameters are automatically added to the CDF list. Now let us say that I added a spectre view of the device, and added those parameters to the CDF list in the by simulation tab, how would that affect the simulation of that device?
Can someone give me an example that illustrates that concept?
Thanks
Hello,
I am sorry if I wrote at the wrong place. (first time)
As a beginner on Cadence (student), I would like to know how to plot transistors parameters (Betaeff, Gm, Cgs, Cdg ...) over a transient simulation.
In fact, I would like to see the parameters values changing over time through a plot. To begin, I have only one transistor.
I've seen other topics, but they last from many years ago (4, 5 or even 8) and I don't understand what people did to plot parameters.
Can someone help me ?
Thanks :)
Hi,
I am using Calibre PEX simulation for post layout simulation. Unfortunately when I load the rules and then trying to setup the inputs, the Calibre gives me the following compilation error. Unfortunately the Rules are encrypted and I can not check the line mentioned in the error message. How can I figure it out?
Regards,
Mehdi
hi
i am simulating a balun with its input/output matching network through HB analysis (using SNP file). While simulating I am getting two different values let’s say V1 and V2. Through SELECT options (" Terminal / Terminal and V- Reference Terminal / Instance with 2 terminals / Port (fixed R(port)) ") i got similar result (value V1) but using " Net (specify R) / Differential Nets (Specify R) " i am getting another same result (value V2). The value V2 is consistent with the time domain waveform simulated through HB analysis. Can anyone please guide me about the reason or mistake that I am possibly making.
Thanks
Hi,
Hopefully this is the right forum to post this...
I'm wondering is there an environment variable I can set to prevent the "stream in translation complete" message that shows upon streamout and streamin completion?
I'm using Viruoso version IC6.1.7-64b.500.8
Thanks,
Brian.
I've been looking over manuals and posts and can't seem to find an answer to this. Can you make one test dependent on an expression generated from another test.
For Example:
Test1 : Find a DC Operating point and measure voltages/parameters. The measured values could be anything you could calculate using the Output Setup and calculator functions.
Test2: Use the calculated results from the ADEXL Test1 Results for the second test.
I know you can do some of this in spectre running multiple tests and saving states but I'd like a more generic/powerful solution. When running across corners this should be done on a corner by corner basis (Test1/Corner 1 feeds Test2/Corner1).
Thanks
I'm trying to design a buffer using tsmc technology file. When I run ADE L , it shows the error below:
*WARNING* feature Analog_Design_Environment_L: ERROR (LMF-02018): License call failed for feature Virtuoso_ADE_Assembler , version 6.170 and quantity 1. The license server search path is defined as 5280@CadenceServer3.localdonain:5280@CadenceServer3.localdomain. The FLEXnet error message is as follows,
FLEXnet ERROR(-18, 0, 0): License server system does not support this feature.
Run 'lic_error LMF-02018' for more information.
WARNING (ADE-5051): Unable to create simulation session.
*WARNING* A check-out of the Artist simulation environment feature failed.
Suggestion: [1] check your license file.
[2] Ask a current user of the feature to exit the Artist simulation environment.
What is the problem here? What are my options?
My Cadence have PVS plugin and my technology library (tsmc) contains assura_tech file. Is there any way to convert those file in PVS compatible format or any other way to use those in PVS plugin ?
thank you
hi
while working on qpsk demodulator i need a qpsk modulated input signal, for which i searched the cadence help and found one telecommunication component with name "QPSK modulator". but i am unable to locate it in library. Can i have any other instance that may give me qpsk modulated signal.
thanks