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Only part of transient time displayed.

May 24, 2017, 3:03 am
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Hello,

I have a similar transient time displayed issue as reported in  https://community.cadence.com/cadence_technology_forums/f/38/t/22201

From spectre.out, the simulation is completed successfully at 1s. However, in the graph window only shows up to 200ms.

Andrew has given a suggestion in the previous discussion (see the link above) of how to solve this problem which requires rerunning the simulation.  May I know is there any workaround without having to rerun the simulation? My simulation took > 12 hours to complete.

Cadence version: IC6.1.4

Spectre version: 7.1.1.187.isr11 64bit

Thanks

Syafiq

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Corner Simulations of Multiple Test with dependent variables in ADE-XL

May 24, 2017, 7:58 am
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I am using ADE-xl to run three separate tests to simulation my bandgap circuit.  One for slope trim, the second for absolute trim, the third for a temp sweep with the proper trim values.  I am able to successfully pass these variables to the multiple test only when i am running a single simulation using "calcVal("Output Name" "Test Name").  When i attempt to run the simulation over corners, there seems to be an issue with the order it runs the tests causing variables to be undefined.  This only happens when i have more than two tests. Is there a way to override the order that the tests are run?

Example run order for a two corner simulation with three tests.

Test1 Corner1, Test1 Corner2, Test2 Corner1, Test3 Corner1, Test3 Corner2 (fail because it has not run Test2 Corner2 yet)

Thanks,

Skyler

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Unbound pins when running Assura LVS in Virtuoso Layout Suite L

May 26, 2017, 4:15 am
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Hi,

I am getting unbound pin errors when running Assura LVS in a layout manually done in Virtuoso Layout Suite L. It seems that Assura LVS is not extracting the pins, which are done in the MET PIn layer with the Create->Pin assistant.

How can I solve this?

Thanks in advanced.

David.

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Access simulation data with OCEAN command getResult() / method description of classType famLeafAnalysis

May 29, 2017, 3:40 am
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Hello,

I would like to iterate through my dcOpInfo results to check automatically for every bsim3v3 instance the region parameter (as an example).


I found the OCEAN report() function. But it does not suit well because I get only a text output.

With the OCEAN command getResult(?result dcOpInfo) I can get a stdobj.

I succeeded also to get the class type/name of this object with:

className( classOf( myRes))

It's name is famLeafAnalysis

and I got also  the class hierarchy with:

myRes = getResult(?result 'dcOpInfo)

L = superclassesOf( classOf( myRes))

=> (class:famLeafAnalysis class:famAnalysis class:standardObject class:t)

foreach( mapcar classObject L className( classObject))

=> (famLeafAnalysis famAnalysis standardObject t)

Now I am stucked. I find no information on these type of objects.

How can I access to simulation data ?

My virtuoso version is:

@(#)$CDS: virtuoso version 6.1.7-64b 05/24/2016 18:54 (sjfbm187) $

Best regards

Hans

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Exporting ADE-L Variables

May 30, 2017, 3:18 am
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Dear all,

I have an ADE-L session which has some variables defined and I would like to export them so they could be used in a script (tcl script). Is there a simple way of  doing it ?

Best regards,

José

PS: Not sure if this is the right forum to ask this....

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stb and tran analysis discrepancy

May 30, 2017, 10:04 am
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I'm having trouble understanding the results of a stb simulation I'm running over process corners and temperature for a basic switched capacitor active integrator.  There is a low frequency pole due to switch leakage/gmin setting depending on the process/temperature which shows up in both the loop gain and phase plots.  What I don't understand is why the phase plot starts at -180 or -90, the phase shift of an (ideal) integrator at DC should be +90 so I'm not sure why the stb simulation shows -180 in the midband.  I'm using ideal switches to short the input and output of the amplifier for biasing at DC and the switches open for the stb portion of the simulation (see the screenshot below).  The voltage source in the DC feedback path is used to precisely set the bias point of the amplifier output.  I looked at transient simulations for some of the corners and the results look great: no ringing, high gain (confirmed by the ratio of the output/input voltage step between phases) and the settling time of in the hundreds of time constants.  It looks like the system should be unstable from the stb results but the transient results don't confirm this, what am I missing?

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What is license feature "Virtuoso_Spectre_GXL_MMSIM_Lk", and how to use it?

May 31, 2017, 1:44 am
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Hi there! Checking the license usage at my site (lmstat output) I find situations like the following for the spectre licenses:

Virtuoso_Multi_mode_Simulation      licenses: 180    used: 159    free: 21
Virtuoso_Spectre_GXL_MMSIM_Lk    licenses: 180    used: 11    free: 169

Al my simulations seem to check out only the "Virtuoso_Multi_mode_Simulation" feature, so I am wondering, what are all those "Virtuoso_Spectre_GXL_MMSIM_Lk" unused licenses? Is there a way I can tell ADE/ADE-XL to use those instead of "Virtuoso_Multi_mode_Simulation"? Often I have a hard time finding enough licenses (a couple of corners for and ADC (using APS) seem to easily check out several tenths of licenses!), so using these instead would be a big help!

Thanks and regards,

Jorge.



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Using DC operating point calculated from spectre in APS Simualtion over Corners

May 31, 2017, 7:39 am
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Hi all.

I have found that Spectre has a better convergence on DC analysis for my specific case. So I'm planning to use DC information from Spectre and then pass it to APS simulator which has better transient performance. 

It could be done easily using writefinal DC value and then read it on APS transient analysis as a node set file. In order to force the sequence of analysis, I have created a dummy variable for a calVal() pass.

However, this approach doesn't work fine when I 'm running corners, because my file is overwritten by each corner run.

How could I read the specific DC operating point for each corner case?

Thanks

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unwanted snapping in layout editor

May 31, 2017, 11:55 am
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Hello,

I am using Virtuoso 6.1.6-64b.

When I draw a 10 um path with metal layer on the vertical direction, then I want to draw another thinner path on it with the same metal layer in the horizontal direction,

the editor force the second path to start from center of the first thicker path, moreover, depends on the direction I am drawing this second path, the editor changes the first path accordingly.

The gravity is set to none, and the options of the path when pressing F3 doesn't show snap to edges or center, just snap mode (orthogonal, diagonal, L90XFirst, L90YFirst)

How can I draw this second path without any modification in the original first path ?

Thank you.

H.A.

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Export simulation results from Virstuoso 6.1.6

June 1, 2017, 5:08 am
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Hi,

I am a newbie in Virtuoso. I have bulk of simulation data which I want to export from Analysis. Individual file handling is too much time consuming. Is there any work around?!
I do not have Virtuoso locally available at my PC. I am running Virtuoso via university server.

P.S. I know there are techniques like .ocn scripts or file handling with veriloga modules, but I am not sure which one is simple and fast. Kindly give your input!

Thanks

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Verilog-A, one time execution function

June 5, 2017, 12:07 pm
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Hi, 

I am developing a verilog-A model for a device. I want to write a function that is executed only one time in the simulation during the device first transition from high resistive state to a low resistive state. I looked at analog events but did not find a function that provides this functionality I want. I tried to do it using an if..else statement but it gave me convergence error. 

Can someone help me with that?

Thanks

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Should I use the PIN or the NET layer for gnd?

June 6, 2017, 5:41 am
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Hi,

I have a layout of a simple PMOS transistor passing DRC, LVS and QRC by using the PIN layer MET1 purpose for the 4 terminals and the connection for the general p-substrate (community.cadence.com/.../37368).

I have some doubts about this because the gnd! connection to the p-substrate is not a PIN in my PMOS cell. How should I implement the p-substrate connection then? Maybe with the NET layer MET1 purpose?

Thanks in advanced!

David.

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Measure DNL/INL in ADE-XL

June 6, 2017, 12:49 pm
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Hi, I am trying to characterize a DAC design and I need to measure these parameters for my design. The way I'm doing it is by sweeping all the input digital codes in a transient simulation. I can use the INL/DNL functions included in the calculator and this works relatively well:

dnl(VT("/OUT") 5e-09 ?mode "auto" ?crossType "rising" ?delay 0.0 ?method "end" ?units "abs" ?nbsamples nil)

but the problem is that the value at time 0 seems to be always 1LSB. When I do optimization or monte-carlo, I want to look at a single number so I'm trying to measure the min or max value of the DNL/INL (using ymin/ymax) to assess the worst-case. Then this 'wrong' value at 0 makes that very hard. I tried setting up a delay inside these functions but the result was the same. 

Any help would be appreciated!

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Problem in importing verilog netlist to cadence

June 6, 2017, 11:28 pm
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Hi,

I am using IC6.1.6 and trying to import verilog power netlist to virtuoso.

I am using File--> Import--> Verilog. My reference library contains digital cells which have pin definitions like @VDD:%:VDD!.

I am getting errors on the import  like

"Error: Can't connect "VDD!" ("[@VDD:%:VDD!]") to non-inherited terminal "VDD!"."

"Error: Can't have multiple net expressions: "[@VDD:%:VDD!]" conflicts with "[@VBP:%:VBP!]""  (VBP is also a  pin defined like @VBP:%:VBP! which is supposed to be connected to VDD!)

I am defining my Power Net Name as VDD! in Global Net Options. Do I need to specify something else as well?

Regards,

Kamran

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How to traverse PSF simulation results programmatically with SKILL/OCEAN

June 7, 2017, 2:42 am
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Hello,

I have the following use case:


- I have a DC simulation with saved operation points in the PSF format in some directory.

- I would like to load the results, traverse the design hierarchy and print out  the vth parameter (as an example for all MOS transistors.

How can I do this with the SKILL language.

I can do it manually with the result browser.

Supposing that the adapter for the tree view in the result browser uses also SKILL, this should be also possible by means of a SKILL script.

I hope somebody could help

Best regards

Hans

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dft error with a valid transient waveform

June 7, 2017, 8:54 am
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Hello,

I want to calculate the dft of a transient waveform.

Thought vtime('tran "/out") is a valid waveform (it can be plotted with no error), I get the following error message:

*WARNING* yvector wrong type.

expression evaluation failed: val is not legal.
expression evaluation failed: dft(vtime('tran "/out") 100n 200n 1024 "Rectangular" 1 "default" 1.0 )
"(\"putprop\" 0 t nil (\"*Error* putprop: first arg must be either symbol, list, defstruct or user type\" nil))"

I tried also with VT("/out"), but the same error appeared.

I am using ic 615isr20121027 and mmsim 15.10.602

Thank you

Best regards,

Aldo

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RE: ADEXL parametric simulation scalar plot

June 7, 2017, 10:39 pm
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Hi All,

         I am using IC6.1.6 version of virtuoso. I want to do a parametric analysis for a scalar value versus temperature. I can do it easily for one corner in ADEL that the scalar varialbe is plotted with respect to my sweeping variable(temperature).But in ADE XL I can run parametric anlaysis but it simulates as individual simulations and I couldn't get the scalar variable plot vs sweeping variable.


I have read some old posts where this facility will be available for IC 6.1.6. So is this option available with 6.1.6? and Is there any other way that I can do parametric analysis across corners like SKILL or Ocean?  If anything please share..

Thanks.

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varying inline subckt parameter with altergroup in Spectre

June 8, 2017, 6:01 am
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I am trying to vary the inline subckt parameter as :

inline subckt n1 (d g s b)
parameters ad=0
n1 (d g s b) n1 ad=ad
model n1 bsim3v3 
ends n1

a1 altergroup {
  model n1 bsim3v3 ad=1
}

But getting the following error :

Error found by spectre during hierarchy flattening.
ERROR (SFE-2201): "input.scs" 20: In altergroup `a1', model `n1'
differs from its previous definition in "input.scs", line 13.

Can I have any workaround for this .

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License server

June 8, 2017, 7:03 pm
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Is there as license server download for Windows 10?

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Layout Netlist and Topcell Netlist shows correct connections but LVS does not pass!!!

June 8, 2017, 8:03 pm
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Hi,


I  am generating the topcel netlist from schematic and layout netlist from layout. I have checked both of them. Topcell netlist has an "X" before each component name which I should eliminate them manually to check the LVS. Netlists show correct connections in the layout but the LVS gives me error and even it says that I have no pins and even the number of nodes are not matched. I have designed a simple voltgae divider and did the layout to make sure whether the problem is with my Cadence or not. But it did not work, too. I have attached my Schematic, Layout and netlists. Please help me since the deadline is so close to me.

Regards,

Mehdi


  Error:    Different numbers of ports (see below).
  Error:    Different numbers of nets (see below).
  Error:    Different numbers of instances (see below).
  Error:    Connectivity errors.

LAYOUT CELL NAME:         test
SOURCE CELL NAME:         test

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               3         3

 Instances:          0         2    *    R (2 pins)
                     2         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         2         2


NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

                Layout    Source         Component Type
                ------    ------         --------------
 Ports:              0         3    *

 Nets:               2         3    *

 Instances:          0         2    *    R (2 pins)
                     1         0    *    rppolyl (2 pins)
                ------    ------
 Total Inst:         1         2


       * = Number of objects in layout different from number in source.



**************************************************************************************************************
                               INFORMATION AND WARNINGS
**************************************************************************************************************


                  Matched    Matched    Unmatched    Unmatched    Component
                   Layout     Source       Layout       Source    Type
                  -------    -------    ---------    ---------    ---------
   Ports:               0          0            0            3

   Nets:                0          0            2            3

   Instances:           0          0            0            2    R(RPPOLYL)
                        0          0            1            0    rppolyl
                  -------    -------    ---------    ---------
   Total Inst:          0          0            1            2


o Statistics:

   2 series layout resistors were reduced to 1.  1 connecting net was deleted.



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