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How to turn off blinking, diamond-shaped markers on the fet geometry in layout

December 3, 2021, 8:49 pm
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Our group has recently switched to Cadence 6.1.8-64b.500.19 from 615, and we updated our design kit accordingly. Opening my previous designs, I see numerous diamond-shaped markers blinking at various places of each FET device in the layout. They are present in both Layout L and XL.

I can't get rid of them using Verify->Markers-> Delete All (No markers match this criteria). I can't find or explain them using ...Markers->Find or Explain. Also I can't get rid of them using Calibre->Clear Highlights (we use Calibre for verification). The layout and schematic pass DRC and LVS. The markers located on the ends of the poly fingers remind me of Weak Connect terminal warning markers. But if they were those, I should be able to Delete them or Explain them; but can't do that in this case. Also here they are present on the dummy polys as well as diffusion contacts, which I've never seen before.

They are so dense that when zoomed out on the full layout, they obscure the layout making it impossible to work. What other switches can I try to see if I can get rid of these, or at least understand what causes them. These markers are only present on fet devices, not general metal routing, resistors etc.

Screenshot is attached. Thank you in advance!

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AC analyses issue in ADE

December 4, 2021, 5:08 am
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HI all,

when I do the ac analyses in the ADE in cadence IC 5141, I set the dc and ac magnitute properly, but I found the node current equation was not satisfied in AC simulation. As the pictures shown below, for example, the sum of the curren in v2, v3 and v4 is not zero! But they all share the same node, is something wrong in the simulation ?

Please help me out.

Thank you in advance!!

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[SpectreMDL] Rise time not founf in transient analysis

December 4, 2021, 8:53 pm
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Hello.

I am trying to perform a few simulations, and I am unable to use the risetime function in spectremdl whereas the same expression is successfully evaluated in the calculator.
Here is my output in ViVA:



Here is the expression that evaluates successfully in the calculator:
riseTime(v("/OUT" ?result "tran") 0 nil 300m nil 10 90 nil "time" )

Here is the expression I have written within a measurement alias in spectremdl:
export real my_rise=risetime(sig=V(OUT), initval=0.0, inittype='y, finalval=0.3, finaltype='y, theta1=10, theta2=90)

Here is how the analysis is defined in the spectre netlist input.scs:
tran tran stop=1u write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5

Here is how the analysis is defined in the measurement alias:
run tran( stop=1u, autostop='yes )

Can someone please tell me if I am making a mistake in either of these places? The calculator I talk about is the one accessed through ViVA (Send to calculator)
The expression successfully evaluates to some value 1.026E-9 as expected from the circuit.

Thanks in advance!

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variables from CDF parameters

December 6, 2021, 3:25 am
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Hello, I have a cell in which the parameters of each instance depend from some CDF parameters of the cell itself.

However the formulas are extremely long, and some instances should refer to the value of different instances.

Example: C1 capacitance is a function of the capacitane of C2, which is defined out of CDF parameters.

Is there a way to refer to C2 within C1? Like an iPar of a different instance.

Pasting the formula used in C2 is of course possible, however the additional operations would increase the length even more.

Alternatively, is there anything like a "hidden" CDF parameter, defined out of other CDF parameters?

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Getting cell name for MOSFET transistor

December 6, 2021, 5:38 am
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Hi all.

I am using IC6.1.8-64b.500.10

I got request to get cell names MOSFET transistors

Can this be done?

Best regards,

Dragan

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ADE Explorer Simulation Error

December 8, 2021, 2:24 am
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Hi,

Whenever I run ADE Explorer it is giving "sim error". The error message that I got from job log is:-

"Failed to launch simulator": "Errors encountered during simulation. The simulator run log has not been generated.\n Possible cause could be an invalid command line option for the version of the simulator\n you are running. Choose Setup->Environment and verify that the command line options\n specified in the userCmdLineOption field are supported for the simulator.\n Alternatively, run the simulator standalone using the runSimulation file in the netlist\n directory to know the exact cause of the error."} 

What is this error? I am running two projects. In older project I am able to work and simulate properly. But in new project, it is showing this error. I have also checked environment setting of both project. They are same.

Please help me to solve this issue.

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calcVal and corner groups

December 8, 2021, 10:03 pm
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Hi,

In performing a set of calibration trim tests, I found a reason I'd like to use corner groups with calcVal.  It appears this is not allowed (per tool manual, in my version, which is IC6.1.8-64b.500.7). 

Here is why I'd like that capability:

At this time I have incomplete specs for a bias current and a reference voltage, which are inputs to my circuit, but I do know their min/mean/max values.  I would like to perform calibration over all 9 combinations of bias and reference, resulting in 9 trim codes. Ultimately this will feed Monte Carlo runs. Later, when the bias and reference blocks are designed, I can simply run calibration tests on them ahead of my block to get actual values for each MC run.

It would be very convenient if subsequent tests could find the matching corner group value to choose the right trim code from the set.

As I read the calcVal documentation, it seems the ?matchParams might do this across multiple non-group corners ("This argument considers the corners and sweep parameters in the same way."), but the ?cornerName will not accept corner groups.

When it is a true single corner, everything works.  When I make a corner group with >1 values to a parameter, I get an error about not finding a corner with the right name (because it is now really a corner group, not a corner, I assume).

Functionally, I'd like this to behave as if a corner group would be matched  correctly and the right trim code gets used when a subsequent test matches the parameters.

I suspect there may be a solution using ?matchParams, but avoiding specifying a ?cornerName,  but I don't see it. Is there a compact way to get this working?

Thanks!

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About Multi technology simulation

December 8, 2021, 11:49 pm
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I think it can be realized by setting all model files in Model library. 

What is different from the MTS option? 

And when I use the MTS option, should I click the button and set Model file one by one to Instances/Cells? I'd like to set a model file automatically to lower hierarchy cells..

""MTS blocks are indicated with a check mark in the MTS column of the Cell Table tab. Click the browse **** button next to a cell to add the path to the model files for the respective technology with which you want to simulate the cell.""

Ichiro

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Edge Triggered Current Source

December 9, 2021, 2:35 am
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Is there a current source available that is edge triggered? The closest thing I've found is isource but the prbs option doesn't give the control I'm looking for. I'm currently using a verilogams model that generates an edge triggered current pulse with a fixed width/amplitude and I'd also like to create a schematic view that accomplishes the same function.

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PSpice model Editor in Spectre and Virtuoso

December 9, 2021, 5:36 am
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Hi All, 

Is there a PSpice model editor is available in the Spectre or Virtuoso to create a model library?

Thanks

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How to merge or hide the metal line from same metal layer in layout?

December 10, 2021, 4:15 am
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In a metal layer, whenever we need to add via than layout add a rectangle across the via areas. So when we fit it to window, layout looks like small rectangle boxes of same metal layer which doesn't looks good and also the continuity of metal looks like it has some disturbance at those areas. Is there any way to hide these rectangle boxes created due to via? Or Is there any way to merge the boundary to metal layer?

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speeding up .hb at a certain stage

December 10, 2021, 3:39 pm
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For a fairly large design, my .pss/.hb simulation spends hours calculating something after the initial transient and before printing the memory estimate. It is not using the multiple processors it is allocated at this certain stage, yet it is taking the multi-core licenses. Does anyone know what spectre is doing, and is there a chance to speed it up? 

I am using Version 20.1.0.186.isr5 64bit -- 27 Mar 2021. 

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Xvfb installation error

December 10, 2021, 9:00 pm
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Hi All,

I am trying to run reliability simulation using IC618 ADE-XL where I am getting the below Xvfb ERROR.

Though I have approached IT team for resolution (which is taking time) is there a workaround so that  I can run reliability simulation using ADE-XL or higher versions of ADE ?

Using ADE doesn't give this error but I cannot perform HB simulations with reliability turned on using simple ADE-L. I need to check the impact on PAE etc... using the reliability simulations.

Spectre version is 20.1

Any solution will be great help.

regards

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Pspice model of memrister running in Virtuoso

December 11, 2021, 10:33 pm
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Hi Andrew, 

Greetings

I'm Ranjan, VLSI student from India. I want to implement the Spice model for memristor into cadence virtuoso in order to implement the memristor into my cmos based analog circuit. Could you please guide me on how can i implement from the beginning? I tried few ways, none of it worked. I would be really really thankful if you could help me with the same.

The above image is the spice code for the model i want to use.( Source: Yakopcic, Phd Dissertation).

.subckt memristor2 TE BE RSV
.params Ron=160 Roff=1200 Th=0.8 Tl=-0.8 Kh1=50e4 Kh2=-15 Kl1=2e6 Kl2=19.75
.func Rt(V1, V2) = IF( V1 <= Th, IF(V1 >= Tl, 0, IF(V2 < Roff, Kl1*exp(Kl2*(V1-Tl)), 0) ), IF(V2 > Ron, -Kh1*exp(Kh2*(V1-Th)), 0) )
Gx 0 RSV value={Rt(V(TE,BE),V(RSV))}
Cx RSV 0 {1}
.ic V(RSV) = 600
Gmem TE BE value = {V(TE,BE)/V(RSV)}
.ENDS memristor2

Also, I have copied in text as well.

Please help me.

Thanking you

Sincerely

Ranjan

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the toxic chemicals...

December 12, 2021, 7:34 pm
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Myself doing lots of DIY had to bury any of my ideas to play around with homemade ICs because of the one crucial step: the chemistry. The toxic chemicals (especially the hydrofluoric acid for the etching which will dissolve bones if not handled carefully) was the point where I would say ... no way. I think the only really showstopper for me were the chems.

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question ： standard cell symbol import to virtuoso

November 29, 2021, 5:43 pm
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I want to import TSMC 65nm standard cell library into virtuoso.

The. SPI file was successfully imported into schematic, but I used xxpwr.v importing symbol, some errors occurred

The following is the error message。

INFO (VERILOGIN-589): Using xmvlog binary for compilation.
ERROR (VERILOGIN-28): Failed to run the xmvlog analyzer because the analyzer binary could not be located.
Either the analyzer binary does not exist in the shell search path or you do
not have the required permissions on the file. Set the correct shell search
path and update the file permissions before running the command again.
ERROR (VERILOGIN-5): Unable to open the specified log file (xmvlog.log) for reading. Either the file does not
exist or you do not have read permission on the file.
INFO (VERILOGIN-206): End of Logfile.
ERROR (VERILOGIN-5): Unable to open the specified log file (xmvlog.log) for reading. Either the file does not
exist or you do not have read permission on the file.
INFO (VERILOGIN-206): End of Logfile.

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is it possible to pass integer to verilog-a module?

December 13, 2021, 3:57 am
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I want to create a verilog-a module that has an integer as input and binary code as output.
it is a DAC, basically.
Later I want to be able to sweep this integer during DC analysis.

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How to report running time of simulation in adexl?

December 13, 2021, 6:49 am
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Hi,

how can I report running time of Monte Carlo simulation in adexl? Is there any built-in function or option to do this? Thank for help!

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What is the Assembler equivalent of loading save output state in ADEXL?

December 13, 2021, 12:26 pm
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With ADEXL if I had multiple testbenches in an ADEXL view and I wanted to replicate the complete output state (save all options + output expressions + nets/currents to save) I could just save an output state then load state with only "output state" checked to the other testbenches.

Now with Assembler to attempt to do the same thing I find I have to descend into the testbench's Explorer view, set up the output expressions I want to save and nets/currents I want to save, and setup the global save all options, then save the outputs as a .csv file.   Then I need to descend into each Explorer view, delete the old expressions and saved nets/currents, load the .csv file, then click on the outputs tab to set the save all options.   This is >> 10X more time consuming than the way I was doing this in ADEXL.

Is there an easier way to do this in Assembler?   Is there an Assembler equivalent to just saving the state in one testbench and loading the output portion of the state to multiple testbenches?

Thank you,

Bill Huff

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How to embed waveform setup (.grf) in maestro views? (or: how to propagate .grf files along with their associated cells?)

December 13, 2021, 2:47 pm
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Hi! is it possible to embed Viva setup information (.grf) in a maestro view, such that it can be version-controlled along with it, thus enabling consistent results display across users?

Or, more generally, how could .grf or .grf.group files be made part of a cell, such that they can be version-controlled and propagate along with it?

Thanks in advance for any help!

Regards, Jorge.

Note1: Our version-control software (Cliosoft SOS) doesn't support .grf files, so they cannot be checked in/out. It works fine without version-controlling by just putting these .grf files inside a folder under the cell directory: the library manager "sees/treats" it as just another cellview, and propagates it along with the other cellviews during e.g. copying/renaming operations; but SOS is unable to check in/out such a cellview.

Note2: I tried creating a Text cellview and overriding its contents with the .grf file; this does fool the version controlling, but has the problem that it can only support one .grf file per view (sometimes we have more) and it cannot support multi-window save waveform setups (i.e. .grf.group), which we use a lot. Also, the Viva file browser doesn't "see" files with extensions other that .grf, so one needs additional steps to actually have Viva load these Text cellviews' contents.

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