Hi Everyone, when simulating the amplifiers that includ current mirror load (diode bias+ current souce), I often meet a strange stb phase plot (figure below):

Sometimes phase rises sharply and sometimes falls sharply, while their magnitude basicaly has no difference.Changing sweep points density, probe location or coner...all these may lead to this "controdictory" result.

Could anyone help explan this phonomeon? thank you!

Spectre 19.1

For example..

(1) I point a node, and then hit any key

(2) Colorful lines fly to all the nodes connected to it (It's not actual wire..it only show the connection info) : "flight line"

(3) I point another node and hit any key

(4) additional new "flight line"

(5) hit another key, disappear all

I always use "view" --> "net highlighting". It's good but I want to keep that trajectory even after removing the pointer.

Thanks

Hi,

I've created a custom dcap PCELL which depending on a parameter value will add a parallel MOSCAP for max cap density or a custom min dummy structure with the intention of minimizing parasitics to substrate to make it more general purpose.

I'm wondering is it possible to conditionally include the MOSCAP when generating a netlist in such a way that depends only on parameter value the user has selected with respect to each of their schematic instances? Perhaps something like below exists?

    cdfId->simInfo->auCdl = '( nil

        ...

        ...

        ...
        condition "cdfgData->parameter->value == valueForInclusion"
    )

I can avoid this maintaining two separate cells so if a work around would be difficult or produce other issues I haven't considered I have a solution.

Thank you in advance and best regards,

Jack

Hi,

I'm doing a DC sweep on a single transistor. I also would like to sweep the lengths and widths.

I have solution for now, but it's highly unsatisfactory, so I would like to be able to exhaust all the possibilities in this forum before resorting to external post-processing.

My aim the following:

- Generate a file per sweep point: each file has the VGS sweep values mapped to an OP param. e.g.: gm

- Each file has 4 columns: vgs and 3x gm for 3 different temperatures

- I'm also doing this across corners. I would like to be able to extract the corner information from the ocean script and append it to the filename.

- I would also like to add other parametric information, such as W or L.

For example, a file would be named "nmos_lvt_W_1u_L_100n_cgs_tt.csv"

And it'd look like this

vgs          -40           ...  135

0.01        1.5e-15     ... 3e-15

0.02       1.6 e-15      ... 4e-15

...

Etc.

So far, my unsatisfactory solution is this one:

1) Generated an ocean script from the maestro TB I did the initial sweep on

2) I added code to extract the small signal params following this snippet's pattern:

selectResult('dc)
resultFile_gm  = outfile("gmid_curves_gm.csv")

gm = getData("M2:gm" ?result 'dc)

drGetWaveformYVec(gm)->expression="gm"

ocnPrint(?output resultFile_gm  ?numberNotation 'engineering  gm)

close(resultFile_gm)  

I apply this to every small signal parameter of interest.

My problem is that, while I get the desired 4 columns, I get the initial corner information which is quite messy and also get more data blocks due to the parametric sweep.

I am aware that with getData(), one can extract also values per corner by using the ResultsDir option. Unfortunately, when I run a simulation, the corners do not appear with their respective names, but only with numbers, which makes it inconvenient as I don't know what folder is which corner.

For example, now I'm sweeping the L with the following code (along with a DC sweep):

but I'm getting my data like this:

I would like to get the 2nd block of data in a separate file with the appropriate parametric info on the filename.

Thanks in advance for your help!

Hello,

I would like to ask you about the criteria of making the size of the pins in the layout design, mainly asking about the supply rails (VDD, GND).

I see from the IPs provided by the company they are covering the metal of the complete rail with the pins.

In my circuit I made the VDD pin just like small rectangular taking part from the VDD connection, I found during the post-layout simulation that the Cadence extraction tool start to consider the IR drop just after the pin, which means that if I covered the complete rail with the VDD pin then I will not have an IR drop. For me it looks like I am tricking the simulation or the reality.

I am using Cadence tools version IC6.1.8-64b.500.6 and assura

Thank you in advance

Best Regards

Hi all.

I am using IC6.1.8-64b.500.10.

I have table with asserts which is generated using asserts .scs file:

Navigating to to schematic for a device that is causing break of assert works by clicking on a device.

As far as I could understand for checks there is option to view critical part in transient analysis graph.

Is there a way, or is it expected in new release, to plot graph for broken asserts regions?

Best regards,

Dragan

Hi all.

I am using IC6.1.8-64b.500.10.

For DC sweeps I can enlarge list of saved parameters for specific MOSFET by creating .scs file and adding it to definition files.

Content of mentioned .scs file may be:

save M0:all

Where M0 is specific MOSFET instance to save parameters for.

Is it possible to do something similar for transient analysis?

Best regards,

Dragan

When i use Medini Analyze software to calculate the chip failure rate, it's support the IP Design.XML file import, IP Design.XML file include the DIE size information.

So, i want to know, how to use Cadence to generate the IP Design.XML file.

Attach is the Medini Analyze use manual introduction.

I'm generating some multipart path templates for shielding and I'm trying to figure out how to implement two functionalities that I don't see in the documentation.

1) The separation for an enclosure should be dependent on the width of the master path. For example if the master path width is < x then the separation for two offset subpaths is y and if the master path width is >=x then the separation for two offset subpaths is z. When I look at the template file generated the width gets hard-coded into the template. I know I can use rodCreatePath() to specify a list of points but that doesn't let you interactively draw a MPP on the layout canvas. I've tried getting more information from the log filter to see what function is being called by the tool when drawing on the canvas but it only shows the mouse click locations.

2) Have an option for either (a) multiple master paths, I'm guessing that isn't possible since the master path is used as the reference for offset and enclosure paths. Or (b) an option to specify a variable number of offset paths. There will always be two paths of a fixed width on each side of the MPP. The idea here is that a shielded bus can be created by specifying the number of routes.

I am learning cadence virtuosuo recently.I installed a tsmc0.18um process library.When performing simulations, it is often necessary toprint dc operating points.

LIke this：（Q2 is a npn of tsmc0.18um process library）

Where can I find the specific meaning of all these parameters?(I tried to use the help function that comes with cadence virtuoso to search. Some parameters can be found, but some don’t. For example, I didn’t find the explanation for ro in the figure above)

Thank you so much.

I have 20 or so DFT expressions that all plot in the same subwindow when I use ADE Explorer. This is handy to quickly compare the magnitude of each.

When I switch to ADE Assembler, each is plotted in its own subwindow. Is there a easy way to have them plot in the same subwindow like with Explorer? Alternatively, is there a quick way to get them all in the same subwindow rather than dragging them one at a time on top of each other? This is Virtuoso 6.1.8_ISR21.

Thanks, Chris 

I have Virtuoso schematics of a "digital" design (down to transistor level) I created 10 years ago, and last looked at 5 years ago. That represents the only times I've tried to run Virtuoso in the last 10 years. The installation I had been using had third party simulators whose licenses are no longer available, so cannot run. I was wanting to eventually export them to verilog (and lose all the work done on the pretty schematics, but such is life,) which would be more useful in the long run. I checked and I have access to licenses for Virtuoso_Schematic_Editor_L, *XL, Virtuoso_ADE_Assembler, *Explorer, *MMSIM_Lk, and a bunch of others. In Linux I tried executing "icfb" like I used to but that doesn't work. "virtuoso" executes but it doesn't look anything like I remember. I tried looking through the documentation, but nothing tells me where the "on-off" switch is, so I feel really stupid. I found a Cadence "Virtuoso Schematic Editor Tutorial" for version 5.1.41, July 2007 online, but it too references "icfb".  Once I get the design open, the exporting may still be a challenge because it looks like the export to SystemVerilog requires a special license. I currently have access to "IC" version v6.1.7. (IC06.17.703). Thanks for any suggestions.

Hi All,

When I update the W, L parameter for any resistor in my schematic it still displays the default or the previous value which is present. This problem is resolved only when I restart cadence and instantiate a new resistor . Can anyone please

help me with a workaround for this?

There are some runs that are missing during monte carlo simulation but if I re-run those specific runs, the results are there.
I am using  IC6.1.7-64b.500.15

Is there any setup that I missed?

This is an example.


this is another example.
In this example, I missed 19 runs.


This is the result after re-simulating only those missing runs.


This is my setting.

An ADE Assembler window is open with one or more tests that are defined and enabled. The simulation has been run and the results tab shows a wave icon for each of the outputs. At this point I want to run a script from the CIW (or from elsewhere if there is a better approach) to plot the outputs. The getData() function will provide access to the psf file from where a wave object can be pulled and then plotted using plot() and this works fine on output signals. An important point to note is that the Assembler outputs setup list can contain long expressions composed of signals that are written to the psf file but the evaluated results of the expressions are not in the psf file. For example the stability factor kf which is a function of the s-parameters generated by the sp simulation is entered into the output expression box as kf(sp(1 1 ?result "sp") sp(1 2 ?result "sp") sp(2 1 ?result "sp") sp(2 2 ?result "sp")) and named myKf. If using getData() in a script I would have to first get each of the four s-parameters and then use them in a call to the built in function kf(). I don't want to hard code all the expressions in the script. I could use maeGetTestOutputs() to grab a string equivalent of the expression but then a non trivial parsing of this string would be required to recreate the function call with the correct arguments. It also seems an inefficient use of a designers time to do some much coding when the expressions have already been defined in the outputs tab and have been already been evaluated.  

Another option might be to use maePlotWithPlottingTemplate() but I want to avoid using templates.           

awvPlotWaveform() looks useful but it needs wave objects as input arguments. So my quandary is how to query the Assembler results database for an evaluated expression and have it return a wave that can be easily plotted?

Hi professionals,

This is from spectre.out log.

What's the meaning of "9" in below? It seems there is not the node9(or port 9) in the schematic...

Matrix is singular (detected at `I1.I2.I3.I4.I5:9' and `I1.I2.I3.I6.I7.AD3<4>').

Best regards,

Ichiro

Hi all.

Does anyone have a SKILL code or method to delete ghost layers that are not visible in  Virtuoso Layout?

Why does it happen?

Thanks.

Jorge

Hi All

the dcblock capacitor in the analogLib shows that the capacitance used in tran is 1u. What would be the capacitance used in s-parameter simulations ?

any hints will be great help.

thanks in advance.

Hi all,

I am using Virtuoso Custom IC design Environment version ICADVM20.1-64b.500.21.

I ran PSS and PNOISE to characterize ring oscillator's phase noise. PSS and PNOISE setup is shown below.

Simulation completed successfully, but it failed to plot "Phase Noise", but "output noise" for saved net can be plot. 

The error message is listed below:

*Error* difference: can't handle (srrWave:0x905e0040 - nil)
<<< Stack Trace >>>
(... in unknown ...)
(... in phaseNoise ...)
(... in pn ...)
pn('pnoise)
(... in _drplOscCornerFreqLabel ...)
(... in unknown ...)
(... in _drplSubmitPlot ...)
(... in _drplPlotButtonCB ...)
_drplPlotButtonCB(asidrplPlotForm51)
(... in geEcStartCmd ...)
(... in astiStartSelect ...)
(... in _drplInvoke ...)
(... in asiDirectPlotResultsMenuCB ...)
(... in sevDirectPlot ...)
sevDirectPlot('sevSession52 'asiDirectPlotResultsMenuCB)
(... in unknown ...)
(... in unknown ...)
(... in _axlADEToolDoWithTemporaryDataDir ...)
(... in unknown ...)
(... in _axlInvokeOutputActionMethod (axlToolAdeAbstract t t) ...)
(... in _axlInvokeOutputAction ...)
_axlInvokeOutputAction("fnxSession0" "tran_8ph_5ff" "/nfs/site/disks/adhdk.work.6/x78a_work/io/yutaoliu/gpsio/simulation/serdesrxclk_adhdk_sim/tb_x78serdesrxclk_clkgen_ro_top/maestro_kvco/results/maestro/Interactive.32/1/tran_8ph_5ff" "sevDirectPlot('sevSession52 'asiDirectPlotResultsMenuCB)" ?history ... )

How can I resolve this issue? Or it there any workaround I can get Phase noise (dBc/Hz)?

Thanks and regards,

Yutao

Hi,

I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bit

I am trying to build a VerilogA model for a (lookup_table) with instance name "I_ACCUM_CLK_GEN_LUT" that is addressed by a modulo (mod_counter) with instance name "I_ACCUM_CLK_ADDRESS_GEN". The read value from this lookup table is then used as clock to another instance of the (mod_counter) called "I_LATCH_CLK_GEN". 

All three instances are instantiated in a parent module (mth_residue_estimator) as shown below:

<code>// VerilogA for behavioral_blocks, mth_residue_estimator, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mth_residue_estimator(in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done);

input in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done;
output out, coeff_done;
electrical in, sk_corr, sk_mult, clk_fs, clk_fs_o_Rp1, kth_estim_all_done, out, coeff_done;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);
parameter real int_clk_skew = out_t_transition from [0:inf);

parameter integer inherent_clock = 1 from [0:1];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];
parameter integer R = 5 from [0:inf);

electrical latch_clk;
electrical accum_clk, address;

lookup_table # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay+int_clk_skew), .clk_f(clk_f), .vdd(vdd), .vclk_threshold(vclk_threshold), .size(R+1)) I_ACCUM_CLK_GEN_LUT (.address(address), .rst(latch_clk), .sk_n(sk_corr), .accum_clk(accum_clk));

mod_counter # (.out_t_delay(out_t_delay), .out_t_transition(out_t_transition), .inherent_clock(inherent_clock), .first_sample_t_delay(first_sample_t_delay), .clk_f(clk_f), .vdd(vdd), .vclk_threshold(vclk_threshold), .clk_dir(-1), .modulo(R+1)) I_ACCUM_CLK_ADDRESS_GEN (.clk(clk_fs), .out(address));

mod_counter # (.out_t_transition(out_t_transition), .inherent_clock(0), .first_sample_t_delay(0), .clk_f(15e9), .clk_dir(1), .modulo(R+1)) I_LATCH_CLK_GEN (.clk(accum_clk), .carry(coeff_done));

endmodule</code>

The mod_counter child module is capable of being triggered by the positive/negative or both edges of an inherent clock (just timers) or an external clock provided via the "clk" input. This is controlled by the "clk_dir" and "inherent_clk" parameters respectively. A generate construct is used.

A @display is used inside each condition to see its inherited parameter values and how the generated behavior will be. All this is shown below.

<code>// VerilogA for behavioral_blocks, mod_counter, veriloga

`include "constants.vams"
`include "disciplines.vams"

module mod_counter(clk, out, carry);

input clk;
output out, carry;
electrical clk, out, carry;

parameter real out_t_delay = 0 from [0:inf);
parameter real out_t_transition = 10f from [0:inf);

parameter integer inherent_clock = 1 from [0:2];
parameter real first_sample_t_delay = 0 from [0:inf);

parameter real clk_f = 3e9;
parameter real vdd = 0.8 from [0:5];
parameter real vclk_threshold = 0.4 from [0:vdd];
parameter integer clk_dir = 1 from [-1:1];

parameter integer modulo = 6 from [0:inf);

integer out_val = 0, carry_val = 0;

analog @(initial_step) $display("Modcounter %M: Instance parameters inhereted are:\n\t\tout_t_delay = %g\n\t\tout_t_transition = %g\n\t\tinherent_clock = %d\n\t\tfirst_sample_t_delay = %g\n\t\t\clk_f = %g\n\t\t\vdd = %g\n\t\t\vclk_threshold = %g\n\t\tclk_dir = %d\n\t\tmodulo = %d\n", out_t_delay, out_t_transition, inherent_clock, first_sample_t_delay, clk_f, vdd, vclk_threshold, clk_dir, modulo);

generate
if (inherent_clock == 1) begin
analog @(initial_step) $display("Modcounter %M: Entering Inherent clock mode because inherent_clk = %d", inherent_clock);
case (1)
(clk_dir == -1) : begin
analog @(initial_step) $display("Modcounter %M: Inherent clock mode falling edge\n\n");
analog @(timer(first_sample_t_delay+0.5/clk_f,1.0/clk_f)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 0) : begin
analog @(initial_step) $display("Modcounter %M: Inherent clock mode dual edge\n\n");
analog @(timer(first_sample_t_delay,0.5/clk_f)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 1) : begin
analog @(initial_step) $display("Modcounter %M: Inherent clock mode rising edge\n\n");
analog @(timer(first_sample_t_delay,1.0/clk_f)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
endcase
end

else begin
analog @(initial_step) $display("Modcounter %M: Enterinng External clock mode because inherent_clk = %d", inherent_clock);
if (first_sample_t_delay > 0) begin
analog @(initial_step) $display("Modcounter %M: Delayed External clock mode");
electrical int_del_clk;
analog V(int_del_clk) <+ absdelay(V(clk),first_sample_t_delay);
case (1)
(clk_dir == -1) : begin
analog @(initial_step) $display("Modcounter %M: Delayed External clock mode falling edge\n\n");
analog @(above(vclk_threshold-1e-3-V(int_del_clk))) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 0) : begin
analog @(initial_step) $display("Modcounter %M: Delayed External clock mode dual edge\n\n");
analog @(above(vclk_threshold-1e-3-V(int_del_clk)) or above(V(int_del_clk)-vclk_threshold)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 1) : begin
analog @(initial_step) $display("Modcounter %M: Delayed External clock mode rising edge\n\n");
analog @(above(V(int_del_clk)-vclk_threshold)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
endcase
end
else begin
analog @(initial_step) $display("Modcounter %M: Non delayed External clock mode");
case (1)
(clk_dir == -1) : begin
analog @(initial_step) $display("Modcounter %M: Non delayed External clock mode falling edge\n\n");
analog @(above(vclk_threshold-1e-3-V(clk))) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 0) : begin
analog @(initial_step) $display("Modcounter %M: Non delayed External clock mode dual edge\n\n");
analog @(above(vclk_threshold-1e-3-V(clk)) or above(V(clk)-vclk_threshold)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
(clk_dir == 1) : begin
analog @(initial_step) $display("Modcounter %M: Non delayed External clock mode rising edge\n\n");
analog @(above(V(clk)-vclk_threshold)) begin out_val = (out_val + 1) % modulo; carry_val = (out_val == 0); end
end
endcase
end
end

analog begin
V(out) <+ transition(out_val, out_t_delay, out_t_transition, out_t_transition);
V(carry) <+ transition(vdd*carry_val, out_t_delay, out_t_transition, out_t_transition);
end
endgenerate

endmodule</code>

When any number of (mod_counter) modules are tested alone at the top level to see if the module acts as expected, it indeed works correctly for all combinations of "inherent_clk" and "clk_dir".

However, when 2 (mod_counters) are instantiated inside the (mth_residue_estimator) as shown above and an instance of (mth_residue_estimator) is tested, I got a weird behavior.

Both counters inside work as if they are in the inherent_clock rising edge mode, i.e., as if "inherent_clock" = 1 and "clk_dir" = 1 which are the default values inside (mod_counter) module, although the values for these parameters are different for both instances during instantiation and the $display statements say that the inherited values are correct.

Basically what is happening is that both instances of (mod_counter) take the parameter values correctly from the parent instantiator module (mth_residue_estimator) and then ignore them totally and use the default values to use in the conditional generate blocks for some unknown reason.

This also happens to any module of (mod_counter) instantiated outside (mth_residue_estimator) but in its presence in the netlist.

I hope someone could help.

Best,

Ahmed