Mutual Coupling

September 15, 2020, 10:53 pm

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Dear All,

I want to build a transformer.

I use "mind" tool from analoglib Library to assign a mutual coupling between two ideal spiral inductors in schematic.

I think it fails with other technology's Inductors, is not it?

I can not use this tool in both schematic and Layout design, is there any solution to build my own transformer in schmeatic and layout as well.

or should I build and simulate it using another EM-simulator and import it in my schematic as (Two-Port) s-parameter file?

Thanks in advance.

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Pin placement is giving me trouble

September 16, 2020, 7:18 am

≫ Next: Monte Carlo Error when simulating larger array (smaller array runs just fine)

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Good evening,

i am trying to automatically place pins in the layout XL enviroment using the Place->Analog->adjust cell pins. But as you can see in the picture below i am not obtaining great results: the automatic tool is placing the pin (the small blue dot at the center of the picture) outside the metal drawing of the net. To me it seems like the tool is placing the pin at the center of an hipotetic big square. I've tried to use the tool place-> Pin Placement and setting the edge as level-1 pin, but it's not working. What i would like to do is to automatically place the pins on its metal drawing, possibily matching the geometry.

I've tried to consult the manuals and the help, but i am able to solve the problem. Do you have any tips?

i am using virtuoso 6.1.7

Many thanks

Best Regards,

Andrea

Monte Carlo Error when simulating larger array (smaller array runs just fine)

September 16, 2020, 9:00 pm

≫ Next: ADE XL Save Options

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I have an array of 64 by 64 simple cells, the cells consist of no more than 10 transistors and their output is either VDD or GND (with mismatch). My problem is when I simulate for 64 rows (with each row consisting of 64 cells), Monte-Carlo throws up an error shown here:

Interestingly when I run for fewer rows, for example 32 rows, Monte-carlo runs fine and I get the expected results. I am not exactly sure what the problem is so would appreciate any help. Thanks.

ADE XL Save Options

September 17, 2020, 7:05 pm

≫ Next: Create a netlist of an extracted view, create a "netlist"/"spectre"/whatever view, and instanciate it in a config

≪ Previous: Monte Carlo Error when simulating larger array (smaller array runs just fine)

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Hi everyone,

I hope to get your help with the ADE XL save options. 

The story is: I didn't change the simulation results save directory, then our lab's disk full. My teacher asked me to change the directory to a local disk. But we all confused with how to set up the Save Options. As the figure below, I change the 'Results Location' to the /local_disk. I clicked 'Use local Simulation Results Directory', but how should I fill out the box below? Its default is /tmp, what does it mean? And how about the ADE XL Results Database Location? Thanks a lot!!!

the following figure is from the adexl window: Options->Save

Any help is appreciated!

Create a netlist of an extracted view, create a "netlist"/"spectre"/whatever view, and instanciate it in a config

September 18, 2020, 5:28 am

≫ Next: ModGen tool is violating the DRC rules

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Hi,

I need to use an extracted view as a subcell in a testbench, and put a resistor of this extracted view in parameter in order to optimize my design with the post-layout parasitics; would you see a straightforward way to do that?

Actually, I was thinking of creating a netist from my av_extracted view as a cell view, edit it to put a parameter on my resistor, instanciate the netlist view in my config, and let's go. But obviously this is not that simple. 

Firstly, how to create a proper netlist easily usable? is it possible to do that without typing text anywhere?

Secondly, how to instanaciate the netlist in a straightforward manner ? I have read the following stuff here: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nXEGEA2&pageName=ArticleContent

...but this is completely incomprehensible for me, as I do not see where we can generate the netlist, and why in 2020 with a multi-thousand $ tool we cannot do that in a simple manner, as I've always seen engineers for about 15 years willing to do that and discouraged by the complexity of the task...

Sorry for my sarcasms...

To sum up, not focusing only on the "create netlist -> modify netlist to add a parameter -> integrate it in a config to run a simulation" supposed by myself, all in all what I need is to get an av_extracted view and put a parameter on one component and lunch a simulation in Maestro with steps on this parameter. Could you please show me the way to do that? Whatever the way?

Thanks a lot in advance for your help, really looking forward for your answers, and best regards.

ModGen tool is violating the DRC rules

September 18, 2020, 6:25 am

≫ Next: Edit Synchronous clone

≪ Previous: Create a netlist of an extracted view, create a "netlist"/"spectre"/whatever view, and instanciate it in a config

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Hello

I am using the ModGen (Module Generator)from Cadence Virtuoso version IC6.1.8

After creating the matched layout array from ModGen and using it in the layout editor, after running the DRC I see that ModGen has created a lot of errors, means he is not considering at all the design rules of our used technology,

I am just showing one selected error in this image where he put the contact vias very near (on the right and lift) that DRC is complaining about

Is there any setting that I have to run before creating routing ?

Thank you

Regards

Edit Synchronous clone

September 18, 2020, 12:33 pm

≫ Next: Is there a way to resume a cadence virtuoso that got stuck?

≪ Previous: ModGen tool is violating the DRC rules

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I am trying to clone resistor chains so they can be all matched.

In the generate clones form I do a search. The tool finds the instances in the pattern mostly.

It selects instance name in other chain. How to I edit the clones found to change the instance name?

When I click edit i can only change the position of the instance under connectivity target menu not the instance name.

Is there a way to resume a cadence virtuoso that got stuck?

September 18, 2020, 4:25 pm

≫ Next: Plot using waveVsWave function

≪ Previous: Edit Synchronous clone

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Hi,

Is there a command or a way to resume a Cadence virtuoso that got stuck due to some process? I am fine with killing the simulation/process that's running on virtuoso but I don't want to kill the virtuoso session and would want to resume that. Is there a way?

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Plot using waveVsWave function

September 21, 2020, 4:17 am

≫ Next: Finfet Stacked CMOS oppoint problem

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Hi,

I've setup an Assembler session with one test and one dcOP analysis.

The schematic is pretty basic, just a single transistor for which vgs, L and W are being swept.

Let's say that I have:

W=1u:1u:10u

W=1u:1u:10u

vgs=0.6:0.1:3

I've set some expressions, such as: OP("M0" "gmoverid"), OP("M0" "vth"), etc

When I right click, on the results tab, the gmoverid result and plot all, it will plot correctly the gm/id curve in function of either W, L or vgs. However if I do the same with the calculator using waveVsWave, it will get the waveform families wrong, that is, it will connect the points to the points of another waveform instead of its own waveform. It seems Assembler doesn't know that that collection of points is a waveform.

How can I get around this? I need to plot any OP expression vs another, like gm/id vs vov, current desinty vs gm/id, etc.

Please check the plots attached (first one right, second wrong).

Thanks in advance.

Best regards,

Pedro

Finfet Stacked CMOS oppoint problem

September 22, 2020, 12:27 am

≫ Next: Can Liberate take encrypted spice netlist?

≪ Previous: Plot using waveVsWave function

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Hi All,

I'm trying to use "Measuring Stacked-FET Parameters" function of SPECTRE16, in order to find oppoint, such as gm, gds.. for stacked Finfet. I have done all settings specified in spectre user manual, and the results shows that except for 'vth' all other params seem to have been correct simulated. But the value for 'vth' is 'nan'.

this is warning for "vth":

Warning from spectre.     WARNING: I0.I16<0>: There is no model param `ivth' for model nch_svt_mac.1, so ignore `vth' output.

Actually I cannot find a 'ivth' param in mosfet models.. How can I solve this problem?

Can Liberate take encrypted spice netlist?

September 22, 2020, 12:51 am

≫ Next: How to export top schematic + all sub schematics?

≪ Previous: Finfet Stacked CMOS oppoint problem

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Hi,

I want to know if Liberate can take encrypted spice netlist, or if this standard cell characterization tool can take encrypted spectre netlist?

Thanks.

How to export top schematic + all sub schematics?

September 22, 2020, 1:33 am

≫ Next: Transient noise analysis - Simulation very slow

≪ Previous: Can Liberate take encrypted spice netlist?

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I am new to Cadence. I was given a design to work in which has many sub-schematics in its hierarchy. I want to export to PDF, PNG or whatever image format the schematic for the top and each sub-schematic in it. I have been looking for this within Cadence IC6.1.8-64b.83. The only option I found was to export the current schematic view as an image. But there are many sub modules for doing this manually. Is this possible?

Transient noise analysis - Simulation very slow

September 23, 2020, 8:55 am

≫ Next: Spectre model aliasing

≪ Previous: How to export top schematic + all sub schematics?

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Hi all,

I would like to run a transient noise analysis in a mixed signal system. For better estimation of the noise bandwidth of interest I ran an AC noise analysis of my system in steady state. I found out that the relevant noise contributions occur below 10 GHz. However, when I'm running transient simulation with noise enabled up to 10 GHz and simulated time over 100 us, the simulation practically takes forever.

Without having any deep knowledge about the transient noise simulation, I came up with the idea to enable transient noise only up to 1 GHz instead of 10 GHz and compensate for the "loss of noise" by scaling it up using the noise scale parameter. I calculate the necessary scaling factor by dividing the integrated AC noise at 10 GHz bandwidth by the integrated AC noise at 1 Ghz bandwidth.

My question is very simple: Is the described methodology to speed up the simulation giving realistic results? Or am I running into trouble here without seeing an important problem?

My idea behind is that, in general, the bandwidth where the noise is generated is of course lower than the expectable 10 GHz, but within this lower bandwidth, I'm scaling up the noise artificially, such that the integrated noise over the full bandwidth ends up to be the sameas if I had simulated it up to 10 GHz.

Thank you very much in advance for your replies!

Spectre model aliasing

September 23, 2020, 1:06 pm

≫ Next: Assura QRC error

≪ Previous: Transient noise analysis - Simulation very slow

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Hi

I have a (I think) really simple question - our spectre models use a name for our transistors but an IP provider used a different name for our MOS that it uses and I was wondering if there's a way to alas the names from the IP provider to map them to our PDK names.

Basically the spectre models we have from the foundry use let's say "nch" for an nmos but the IP provider uses "N" in their spectre netlists.  Since it's a standard cell library it uses the model a few million times and since it's a proper foundry provided spectre model it also references the models a few other bajillion times...basically is there a way to create a short in the spectre definition that will map these models together since they're the same MOS?  I need to do this for both P and N.

Thanks

Chris

Assura QRC error

September 23, 2020, 6:57 pm

≫ Next: would it be possible to copy a component or block inside a symbol when you descend into a block and copy it out?

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Hi everyone!

Recently I'm using Assura and  I can run drc and lvs

However, qrc always fails. The log file gives errors as follows:

I run the cmd terminal>$QRC_HOME/tools/bin/RCXspice -args in a terminal window and it give a long list of cmd options

 I would appreciate if any advice could be offered.  Thanks.

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would it be possible to copy a component or block inside a symbol when you descend into a block and copy it out?

September 25, 2020, 4:48 am

≫ Next: Noise Contribution and Simulation in Cadence.

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In schematic, would it be possible to copy a component or block inside a symbol when you descend into a block and copy it out?

Like first you use "shift + E" to descend inside a block and then use "c" to copy it and then ascend with "ctrl + E", paste it on a schematic outside?

(Virtuoso version IC6.1.8-64b.500.8 )

Noise Contribution and Simulation in Cadence.

September 28, 2020, 4:18 pm

≫ Next: bindkey to open calibre nmDRC & nmLVS & PEX

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Hi, 

I would like to know how to simulate noise simulation in cadence, I am trying to simulate a simple current mirror and trying to find how much noise it contributes to the circuitry. I biased the current mirror as per my requirement and added a pin at the output in the schematic where it has to go inside the circuitry. I am using noise and noise separation analysis. Also, I would like to know how to read the Noise Summary from Print and in the Plotting of the data. 

bindkey to open calibre nmDRC & nmLVS & PEX

September 29, 2020, 2:44 am

≫ Next: Is there some way to calculate power consumption of blocks in a schematic automatically?

≪ Previous: Noise Contribution and Simulation in Cadence.

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Hi, is there bindkey to open nmDRC, nmLVS and PEX in Calibre from layout view?

Thanks for your help. 

Is there some way to calculate power consumption of blocks in a schematic automatically?

September 29, 2020, 1:42 pm

≫ Next: Plot horizontal line (e.g. limit line) in ViVa

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Is there some way to calculate power consumption of blocks in a schematic automatically?
Power consumption is calculated by voltage* rms(current) over a specific period.

I saw the code for I0:pwr but this is only for static power instead. 

Plot horizontal line (e.g. limit line) in ViVa

September 30, 2020, 1:16 am

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Hi,

I want to add a horizontal line to the ViVa plot (e.g. for a transient plot).

I do not want to use the "h" button in ViVa.

I want to define the y-value of the line via output expressions as a function of a design variable.

How can I do that ?

BR

Holger