Hi,
I have been simulating the VCO, the frequency and voltage calculated from the tsab simulation varies from the PSS simulation? Why is that so?
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Why the tstab and PSS simulations differ in terms of frequency and vrms voltage?
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Run QRC using commd under batch mode
Hi
I using cadence version 6.1.8, may I know do I need any license to run QRC using command?
please advice.
regards
Faisal
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IBIS model from Virtuoso
Hi All,
can anyone give any insights on if there is a way to generate IBIS model of an IC design from Virtuoso itself perhaps from the Spectre netlist ?
It can be done is other external tools but I wish to check if it is also possible without moving out of the Virtuoso framework ? And if there are any additional licenses required for such a feature.
thanks
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Problem in running QRC Quantus in Cadence Virtuoso
Hello,
We Newley installed our PDK, when I try to run the QRC I receive the following error message,
Is it harmful to ignore ?
Thank you very much
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How to customizing library manager menus
I tried to add a custom menu the library manager, and can't get it working. It looks to me like the cdsLibMgr.il file is not being loaded. I tried adding this line to it, but nothing shows up in the lib manager log...
printf("hello")
However, when I type the below into the main Virtuoso window, it reports the right file path. I even tried changing the path to an absolute one (and confirming it picked it up with the below), and it still didn't seem to pick it up. Any ideas?
envGetVal("cdsLibManager.customize","startupFile")
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LVS with backend kit
I'm trying to LVS a design made using a backend kit.
There's main part of the design was created in the analogue flow which lvs's as every cell has schematics.
The top level of the chip has some standard cell logic cells that have no schematic view, and a digital block created in encounter (this has verilog code associated with it)
I've tried to black box the cells in calibre, but I'm afraid my knowledge of how to do that isn't up to snuff.
Can anyone lend me some advice on how to LVS such a design?
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Genus - Hierarchy
Hi,
I am building my circuit which involves a top level and several sub-modules.
I am interested in details about these sub-modules, but after the synthesis (syn_generic), the hierarchy is lost and I can't access these sub-modules any more.
Any ideas?
Thanks
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Print statements with subcircuits
Hello, I have a question regarding spectre netlist language
I know If I have a circuit containing MOSFETs, I can use a print statement to save specific parameter value to a file with the following statment:
print M0:vth,
+name = dc addto = "myfile.txt"
I wonder How can I use do the same If my mosfet now is defined inside subcircuit I?
I see nothing about this in spectre help
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White Noise simulation for MOS transistor
Hello,
How is it possible to determine the white noise of transistors from simulation?
I know how to determine the noise at the output of transistors for flicker and shot noise but not for white noise.
Thanks a lot in advance.
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Intrinsic and extrinsic capacitances from simulation
Hello,
In DC simulation it is possible to save DC operating point parameters to determine extrinsic and intrinsic capacitances. For example, CGG = cgg + cgsol + cgdol + cgbol, CGB = cgb + cgbol, CDD = cdd + cgdol + cjd and for the junction or depletion capacitances such as CDB from hand calculation
Cdb={(AD*CJ)/(1+Vdb/PB)^MJ)}+{(PD*CJsw)/(1+Vdb/PB)^MJsw)}
Cdb= Area contribution + SideWall contribution.
1. AD and PD are the Area/Perimeter of the drain junction
2. Vdb is the Drain-Bulk voltage
3. CJ, MJ, CJsw, MJsw, PB are process parameters you can get either
from your model card or from any document that is provided by your
foundry:
-> CJ=Zero-bias junction bottom capacitance density.
-> MJ=Bulk junction bottom grading coefficient.
-> CJsw=Zero-bias junction sidewall capacitance density.
-> MJsw=Bulk junction sidewall grading coefficient.
-> PB=Bulk junction built-in potential
How is it possible to obtain the value of CDB from the simulation? is it going to be CDB = cdb + cjd. And how about CDS?
Thank you so much in advance.
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Calibre view generation encountered a fatal error
Hi,
Has anyone experienced this type of error? I cannot generate the calibre view. The calibre log file states that my library can't be found although the parasitic extraction is performed.
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Does IC618 work in RHEL 8.2?
Hi,
I have checked the compatibility matrix document. I’m trying to understand when it says IC618 runs at RHEL 8, does it mean it works with the minor releases of RHEL for example 8.2?
Second thing is, where should I look for IC617 (in fact old versions of any tools)? In the downloads I only can see IC618.
Third, if I install the base then on top of it, installation just the hotfix is fine or I have to install updates also? Does installation of hotfix work?
Thanks for your time!
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IC617 Running Issue at RHEL8.2
Hello,
First of all, I understand that RHEL 8.2 is not a supported version for IC617. But, as I already installed the Hotfix_IC06.17.722_lnx86.sdp (I haven't installed the base) and later figured out the compatibility issue, I like to see if it works before I reboot my system with other supported version of RHEL. I used Installscape for the installation and choose install from the local directory. But I got an error as it complains about the OS. I am adding snapshots of the errors I got. I would appreciate any suggestions.
Here is a pic of my startup.ic6 file:
Thanks a lot for your time!
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ADE: is it possible to select DSPF nodes for PNOISE simulation?
Hi! I am trying to run a triggered PNOISE analysis on a extracted design using a DSPF view, but I'm unable to specify in ADE the triggering nodes.
In my original PNOISE settings (run over the pre-layout schematic) the trigger event is defined on the following nodes (which I selected with the mouse on the schematic view):
/DUT/LATCH<5>.vOUTp and /DUT/LATCH<5>.vOUTm
which the netlister translates into the following directive in the netlist:
pnoise pnoise start=SIM__FREQDOMAIN__Fstart stop=SIM__FREQDOMAIN__Fstop \
dec=SIM__FREQDOMAIN__Npoints_per_decade pnoisemethod=fullspectrum \
noisetype=sampled measurement=[pm0] annotate=status
pm0 jitterevent trigger=[DUT.LATCH\<5\>.vOUTp \
DUT.LATCH\<5\>.vOUTm] triggerthresh=(PNOISE__vREGENd) \
triggernum=1 triggerdir=rise target=[DUT.LATCH\<5\>.vOUTp \
DUT.LATCH\<5\>.vOUTm]
However, when I try to switch to the DSPF view for my DUT (using a config view), I cannot specify anymore the above nets for defining the PNOISE trigger.
I tried, without success:
- To manually type the node names in the ADE PNOISE dialog; but when I press the "change" button, ADE complains (e.g. "Couldn't find net named "DUT.LATCH\<5\>.vOUTp" in the design")
- To copy the pnoise analysis definition in a text file and pass it to ADE as a .scs model file; but the netlister includes it in the netlist before the PSS definition, so Spectre ignores it (because it didn't run first a PSS)
Any helps is greatly appreciated!!!
Thanks and regards, Jorge.
P.S. Apparently someone had the same problem long time ago:
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How to group design variables and switch between them for different tests in ADEXL
Hi,
I am trying to run different simulations(tests) for the same schematic in same ADEXL view. In other words, I have a single schematic and ADEXL view. In ADEXL view, I have couple simulations tests.
What I need to do is to have different controls(design variables) for the different simulations in the same ADEXL. With local variables, I can assign individual variables for each tests but what I need to do is to have a group of design variables changing for each tests. Grouping design variables is not working for local variables.
One way can be to include a file which has sets of design variables for each tests. The selection can be done with another design variable but I am not sure how to tell ADEXL to run parameter sweep based the info from that file since grouped variables are more than one sweep.
Thanks
yayla
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How to evaluate the variable in a maestro measurement expression and not treat it as a literal string
I am trying to measure some signals and it is constantly evaluating it as a string and not capturing it as a variable
Example:
This scenario works perfectly --> maeAddOutput(strcat("read" "avg") title ?outputType "point" ?expr "average(VT(\"/net_read\"))")
But I am trying to use a variable for the signal name, how can I achieve that.?
Example: name = “net_read”
maeAddOutput(strcat("read" "avg") title ?outputType "point" ?expr "average(VT(\"/name\"))")
How can I tell it to replace name with the variable because it is currently processing name as an input signal and not the content (net_read)
What is the correct syntax to insert variable in a maestro measurement expression
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lost file
Hello everyone!
Iv designd an ALU as part of school home work, after creat all small parts Iv created the ALU - schmatic and layout.
After the file had pass DRC and LVS with no errors i tried to have a QRC check- than, with not paying attention, i choose to overwrite somting and my ALU have lost!!
now it seems there where nothing in the ALU file- no schematic and no layout files.
What can i do now? there are any way to restore the fiels??
hope someone can help me! regards.
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LVS reads pins incorrectly
Hello,
I am running an Assura LVS test on my layout and receive some mismatch errors like the following:
Schematic Net: S[0]
S *1 of device_X:Swap1 A
Layout Net: S[0]
L *1 of device_X:Swap0 C
Clearly the issue LVS brings up is that S[0] pin is incorrectly connected in the layout, but as can be seen from the screenshot, S[0] is connected to net A and not C as LVS claims.
There are a number of devices in the layout, the problem happens on the "device_X" only. The problem happens to more pins (but not all) in the "device_X". I tried to run all sorts of Updates from the Connectivity menu. Tried deleting the device and regenerate from source. Even tried to do a completely new layout of the problematic device, but to no avail. Does it have to do with this "Swap0\1" after the device name? What is the meaning of these swaps?
Please advise
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ERROR ADEXL 7514
Hi,
Every time when I open the assembler, and try to view the existed result, terminal shows me the ERROR ADEXL 7514 as below, also my assembler window is stuck. What is the root cause and how to remove this ?
BR
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Transformer and Mutual Coupling
Dear All,
I want to use a transformer in both cadence spectre and virtuoso,
My used Technology does not have its own Transformer.
How I can Activate the mutual coupling between two Technologu's spiral Inductors in schematic and layout as well.
is this possible ?
or I have to build my own transformer using another EM-simulator and then importing its S-parameter block to the cadence environment.
Regards
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