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unbound variable - device property issue

August 20, 2020, 1:14 am
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Hi,

I set a variable "L350" to NMOS transistor length and sweep the variable. It works well. 

However, after I try parameterization on its length, accidently cds shows the unbound variable issue of "L350", CIW report: CDF parameter function has problem. And when I open property of NMOS transistor by "Q", all CDF info disappear. 

I can forcely open property assistant view, and find many yellow exclamation mark as below. Btw, the netlisting and simulation still work with this issue. 

Is there anyway to recover the CDF settings as before? Thanks!

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CMRR simulation setup

August 20, 2020, 8:54 am
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Hello,

This question has been asked multiple times and answered here: https://community.cadence.com/cadence_technology_forums/f/rf-design/27951/plotting-cmrr-and-psrr-in-cadence-virtuoso and 

here: https://community.cadence.com/cadence_technology_forums/f/rf-design/27951/plotting-cmrr-and-psrr-in-cadence-virtuoso/1329716#1329716

I set up my simulation test for CMRR as follows:

I used the xf analysis and the result doesn't seem right. 

Here is what I get:

I even took the reciprocal of the above response and it is not coming right.

I also followed this popular method and it didn't work. 

 

What am I doing wrong?

Thank you so much in advance. 

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How to load different .dc file for each corner in single run

August 20, 2020, 1:18 pm
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Hi,

this might not be an urgent issue, but I'm wondering how I can treat corner as a variable, and apply different file reads for each corner.

I'm sweeping corners with dc+hb analyses, and SS@-40C has convergence problem at dc. Therefore just for this corner I'm running dc at 25C, and hb at -40C (which is tolerated in my work).

The corner setup window will look like this.

While keeping this setup, I separately run dc at 25C, save it to a 'spectre_SS_25.dc' file, and load this file when I'm running hb at SS-40.

The rest of the corners will follow nominal setup, where dc saves spectre.dc and hb loads spectre.dc in the same directory.

My question is, can I do this setup in a single run? Right now I have to run a separate simulation for SSm40.

The pseudocode will be something like, 

if corner==SSm40, readic "spectre_SS_25.dc", 

else readic "spectre.dc"

I'm new to SKILL syntax so I don't know what the right expression is, or if it's allowed at all.

Thanks for the help!

Joon

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Adding menu to Layout WINDOW

August 21, 2020, 12:23 am
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Hi All,

I am using a legacy skill code that adds a menu when the design in opened in Layout XL but not when it is opened with Layout EXL.

In short the custom menu doesn't appear when using Layout EXL , can you please suggest what could be the possible reason ?

regards

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**WARN: (IMPESI-429): No RC available on net xxx in INNOVUS 19.13

August 21, 2020, 2:48 am
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Hi,

during optDesign postRoute log show a lot of warning IMPESI-429, what could be the reasons? 

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Can't add DC parameter via the annotation

August 21, 2020, 2:29 pm
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Hello,

This question has been asked multiple times as shown here:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/41046/unwanted-empty-line-in-annotation-setup

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42253/can-t-edit-value-of-cdf-parameters-in-edit-object-property-form

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/42253/can-t-edit-value-of-cdf-parameters-in-edit-object-property-form

I followed the instruction by going to CIW > Tools > CDF > Edit and did the following:

1. Scope selected cell

2. CDF Layer selected Base

3. Library Name the desired library is chosen 

4. Cell Name the preferred Cell name is selected 

5. I am confused on callback setup 

6. From the tab, I chose Interpreted Labels 

7. Use CDS parm to display selected operating point results and added region

I am attaching two pictures. The first one is what I get on the annotation balloon and the second picture is what I did to select the region dc parameter. But for some reason, region is not showing on the transistors. 

I consulted the PDK documentation, and I couldn't find anything. 

Thank you so much for your help.

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LVS not able to read layout with hierarchy.

August 22, 2020, 3:10 am
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Hi
 anyone know what happen why lvs result show it missing basic cell like P_18_ICS_MM . please advice.
1. (without schematic hierarchy) We create new layout for SL_PARINV.  As yau can see below. LVS result for  SL_PARINV it self is clean.

2. (with schematic hierarchy) We create new SL_PARINV with hierarchy schematic.and the lvs result show it missing
 basic cell like N_18_CIS_MM. from my point of view its like the lvs not able to read connection from layout that have hierarchy.
please advice.
regards
Faisal.
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Floating Vpulse Influence Simulation Result

August 23, 2020, 12:53 am
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Hello

I get confused recently. I am simulating a DCR (Direct conversion receiver) to get the output DC term caused by second order non-linearity of it. And I find a weird phenomenon, that is the vpulse can influence the simulaition result even if it only connects to ground. I change the frequency of it, and the simulation results changed. Is it a BUG? or something impossible?

Did anybody meet situation like this?

thanks

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fail to open the cell after copy its full directory

August 24, 2020, 12:27 am
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Hi, I munally copy a cell's directory (veriloga + symobl) to my own directory in windows. 

After opening my cadence, i could see the cell in the lib manager, but both veriloga and symbol views are not able to open (the open option is gray).  Also I can not include them in my design. 

Is there anyway to solve?

Thanks for your help. 

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Renormalize S-Parameters

August 24, 2020, 6:25 am
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Hello,

is it possible to renormalize S-parameters to another reference impedance? I could not find an option for the 'sp' simulations or a function, which allows me to change the reference impedance of my S-parameters.

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editing input.scs not working in Assembler

August 24, 2020, 8:50 am
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Hi,

I am running IC6.1.7 and sometimes I need to edit the simulation netlist (for example to add a parasitic cap). One issue that I have is that I am using Assembler and it automatically generates a new "input.scs" file everytime hit simulation ->run.

So what I do is I go to the simulation directory, modify the input.scs, and then run the simulator standalone using the runSimulation command in the netlist directory. The problem is that when I load the PSF file in "Result Browser" the results are the same as before editing the netlist (it seems that the simulation didn't use the modified "input.scs" file!! 

I would appreciate your comments on this. 

Best regards,

Hasan

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Change the plot background to White

August 24, 2020, 5:05 pm
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Sometimes, I want to take a screen shot of the plot in cadence for documentations. Black background is not clear after taking the screen shot. I can change it to white background. But when I change to a new plot, I have to set it again. 

I am wondering if there is a way to set the default plot background to white so that all my plot back ground will be white.

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measuring set up time for a DFF

August 26, 2020, 9:12 am
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In my simulation, the D input to the flop consists of random data.  I would like to measure the time between each transition of data to the capturing clock edge.  It is not hard to trigger on the crossings for data but I have a hard time to set the stop time as the subsequent clock edge.  I have tried as many variants of the Delay function that I can think of but none seem to work.  

Here are example waveforms.  The goal is to find the minimum set up time for a long sequence of events.

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Problem with SwapSweep

August 27, 2020, 1:14 pm
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Hi,

I am trying to plot the frequency of an oscillator as function of its control voltage, the expression in Calculator is like below

swapSweep(freq(v("/oscout" ?result "tran") "rising" ?xName "time" ?mode "auto" ?threshold VAR("AVDD")/2) "vtune" 4e-07)

This works well when I plot it from Calculator. But when I send it to ADE (maestro Outputs Setup) and click re-evaluate, I get an error as below:

INFO (ASSEMBLER-2328): Following error occurred while re-evaluating output F_vs_vtune :
*Error* _drSwapSweep: (CALC-3): Cannot perform the Swap Sweep operation because the input waveform is not a parametric waveform.

What is wrong?? 

Thanks!

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Cadence IC6.1.7 Installation Manual

August 27, 2020, 8:33 pm
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Hello,

I want to install Cadence IC6.1.7 (Custom IC / Analog / RF Design)and Mentor Graphic Calibre tools on RHEL 8.2 server. I want to make the following things work after the installation:

1. Circuit Design: Virtuoso Schematic Editor

2. Circuit Simulation: ADE-L, ADEXL using Spectre simulator

3. Layout Design: Virtuoso Layout Suite L, XL, GXL

4. Layout Verification: Mentor Graphics Calibre: nmDRC, nmLVS, xRC

Where should I find documentation to fulfill the tasks? 

Thanks!

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Ringing in transient simulation.

August 28, 2020, 12:07 am
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Dear all,

I encountered an unexpected ringing while running transient simulation for a high-speed receiver.

I am using ADE Assembler and the version is ICADV12.3-64b.

The detail is as following,

There are CTLE, source follower, interleaving switch and SAR ADC in series in my test bench. The differential input of CTLE is proved by an ideal voltage source through 50Ohm ideal resistor.  And there are also 8 "vpulse" voltage source realizing 8 phase 8GHz clock driving interleaving switches. There is some s-parameter file to model the induction inside CTLE. And there are a few tens of ideal voltage sources providing dc control signals. I saw unexpected ringing on top of the CTLE input signal in the transient waveform.

In order to debug this issue, I remove all circuitry after the source follower. So there are only input voltage source, CTLE, source follower and 8 clock voltage sources (which are open), and some dc control voltage source in the test bench. The ringing remained there.

If I removed those 8 clock voltage sources in the schematic, or did not save their waveform , the ringing went away.

Below is the my transient simulation setup parameters
start = 0 s
outputstart = 0 s
stop = 10 ns
step = 10 ps
maxstep = 200 ps
ic = all
useprevic = no
skipdc = no
reltol = 1e-03
abstol(V) = 1 uV
abstol(I) = 1 pA
abstol(U) = 1 u
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS
rabsshort = 1 mOhm

Do you have any idea about this issue?

Thanks and regards,

Yutao

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How to measure output power in dBm of an LC tank VCO?

August 28, 2020, 1:38 am
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Hi, I would like to know how to measure the power of an LC tank VCO? I have seen the spectre RF workshop document, The PSS simulation is performed they have kept the R value to 10 kΩ. I don't understand the logic behind it. We shall measure with respect to default value i.e. 50 Ω load. Anyone who has performed this kind of simulation? The snapshot below is attached

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Difference between some dc parameters on spectre user manual

August 28, 2020, 10:16 am
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Hello,

I am looking at the spectre user manual for IC6.1 and I see the following parameters:

u: transistor gain no unit given

self-gain: transistor gain with no unit given

fug: unity gain frequency at actual bias in Hz

ft: unity gain frequency at actual bias in Hz

These are given on page 2106 for PSP103 model which I am using. 

I know that in some literature ft which stands for the transit or transition frequency is ten times the fug (unity-gain frequency). How about they and self-gain? Do they mean the same thing?

My Virtuoso version is:

Version IC6.1.8-64b.500.9

Spectre191

Thank you very much in advance.

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Spectre RF Application note question

August 30, 2020, 7:25 pm
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Hello, 

This is regarding the following application note which I found in the spectre RF workshop directory.

Spectre RF: PSTB Analysis Application Note from December 2013.

It does examples of RF simulation and mentions "to open a schematic for the oscillator_sckt in the library PSTB. Where is the library located at?

My Virtuoso version is:

Version IC6.1.8-64b.500.9

Spectre191

Thank you so much in advance.

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Net tracer feature

August 31, 2020, 3:44 am
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Hi All,

can anyone please let me know if Net tracer feature can be used to extract a complete net across the different metal layers into a separate GDS only for that signal net ?

regards 

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