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Getting/highlighting all input pins of a design in schematic
Hi,I am working on a huge schematic in virtuoso with lot of pins. I wanted to know if there is any way that I could highlight or get a list of all the input pins only in the design.Thanks,Sunny
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SPICE imported .SUBCKT requires different modelname than given in netlist
I do have a PDK library with an nmos device with different device and model namelibname= <pdk lib>cellname= nmos_1p5_dwmodelname= nmos_1p5 <-- this name is provided by the modelfileThat is...
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Plot depended design variable for a simulation with variable sweep
Hello,I guess this question is not new, but I could not find any solution so far.I am using maestro and I have a frequency simulation (eg. ac) where I sweep a design variable 'x' at a fixed frequency....
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Parameterized Instance Array in Schematic
Hi,How can one set the length of an instance array as a parameter in Virtuoso schematic? If instance array is thearray<4:1> it instantiates 4 instances but how can one set the "4" as a parameter...
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Simulation Determinism
Hi,I have an AMS/Spectre simulation that I have run twice, by starting them 45 seconds apart in time, on the same multi-core machine in a simulation farm of machines, using the same number of cores....
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Total Perimeter of a Layer on the Layout
Hello,I use IC6.1.7 and Assura 4.15.I would like to get the total perimeter information of a specific layer on layout. Is it possible? During this calcualation, the decrease of the perimeter due to the...
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measure ripple voltage and current
I am using Cadence 6.1.8 release and I am using ADE Explorer. I am working on a chopper amplifier and need to measure the ripple voltage due to the chopping. Is using peaktoPeak function and clipping...
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Probing nodes in sub-hierachies with SPF
Hi guys,I got in my head that with Spectre X (Spectre 19.1) we should be able to probe voltages and currents on sub hierarchies while simulation with SPF files, without having to modify the probes to...
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how to exclude a net in Quantus parasitic extraction
Hi,I wanted to know how I can exclude a net and/or Power nets from extraction in Quantus. It seems that we can exclude power nets from extraction under "filtering > Enter power Nets" but that...
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Prevent simulation of specific cell views
Hello,I have a cell for a layouted cell, which contains a schematic and an extracted view. The schematic is required for LVS and must be called 'schematic', but it should not be simulated directly. Is...
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ADE-XL response very poor when running large monte-carlo simulation
After submitting e.g. a large MC run I find that the ADE-XL window (and in fact the whole Virtuoso session) has very poor response. Basically the whole session is virtually unusable until the...
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INL simulation issue for temperature sensor
Hello,I would like to determine the temperature error of my temperature sensor circuit by using a viva function integral non-linearity of a dc temperature simulation. I want to show the output voltage...
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Ultrasim DSPF Stitching Failed
Hi,Recently, I want to run post-layout simulation using Ultrasim, futher more I want to using xrun+ultrasim to run co-sim.But from the simulation results, it seems DSPF stitching failed, because the...
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plotting expressions of multiple tests on the same Viva window
Hi all,is it possible to plot several expressions (let's say the "conjugate(S11)" like in the example below) belonging to different tests ("...dieID_01", "...dieID_05" ) on the same window in VIVA...
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Bottom Up Hierarchical Design
I was reading through Cadence tutorial on how to create a bottom up design i.e. starting with low level board schematic then creating a higher level schematic, however I'm not able to do this properly....
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fully differential opamp stb simulation
Hi teamThe schematic of the fully differential amplifier is in the attached pictures. I want to simulate the differential gain/stb and common mode feedback loop stbFig1 fully differential amplifier...
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Transient noise simulation does not converge
Hello,I am running transient noise simulation on my circuit (Clock tree with square wave source)i am using moderate errpreset, reltol, vabstol and iabstol and gmin are all the default values.the...
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plotting more than one variable on x-axis in viva
Dear All, One question : I would like to put more information in one plot. Means for example if i have simulation results for voltage across corners and temperatures than i would like to plot this...
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Finding area of the designed schematic
Hi,Can anyone help me on how to find the area of a designed circuit from schematic in Virtuoso. I designed it in 90nm CMOS process technology using gpdk90. The schematics is the following.
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