Accurate delay measurement between two clocks
Hi,I am currently struggling with measuring the delay between two clocks with a sufficient accuracy. The reference one is a fixed-phase clock, and the other one is a squared clock resulting of a...
View ArticleERROR (SPECTRE-308)
HiI have this error when I run the simulation SPECTRE_DEFAULTS=-I/CMC/kits/tsmc_130nm/CR013G/PDK_OA/PDKOA33/models/spectre -f psfbinCommand line:...
View ArticleISF Function Extraction in Cadence Virtuoso
Hi all,Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?Thank you.
View ArticleVirtuoso Spectre Monte Carlo simulation
Hi , I have designed analog IP in cadence ADE and simulated in spectre. All corner results looks good. when i run monte carlo 1000 runs have high current in 125C two runs. Simulated with same setup...
View ArticleRegarding Save/Restore Settings for Transient Simulation
Hello,I am running a transient simulation on my circuit and usually my simulation time took me more than a day (The circuit is quite big). I am usually saving specific nodes to decrease the simulation...
View ArticleUnable to Import .v files with `define using "Cadence Verilog In" tool
Hello,I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.When I use the...
View ArticleUsing calcVal() in Monte-Carlo simulations
Hello,I am trying to use calcVal for creating a spec condition from a simulated parameter and although this works perfectly fine in corner simulations, I am having some difficulties in Monte-Carlo (and...
View Articleconvert ircx to ict or emDataFile for Voltus-fi
Hi,I want to convert ircx file(which from TSMC) to ict or emDataFile for Voltus-fi.I tried many way, but I can not make it.and I do not installed QRC.below is some tools installed my server....
View ArticleSimulating PSSR+/PSSR- and CMRR
Hello,I would like to simulate the PSSR+/PSSR- and the CMMR using xf for the attached test bench.Normally, I do the AC analysis and using the post-processing capability of cadence spectre I do...
View ArticleCan't Find Quantus QRC toolbar on the Layout Suite
Hi, I want my layout verified by Quantus QRC. But, I can't find the tool bar on the option list ( as show in the picture)I have tried to install EXT182 and configured it with iscape already, and also...
View ArticleLayout can't open with the following warning message in CIW
Hi,I tried to open my layout by Library Manager, but the Virtuoso CIW window sometimes pops up the follow WARNING messages( as picture depicts). Thus, layout can't open.Sometimes, I try to reconfigure...
View ArticleSimulating IBIS Model using Spectre
I have a question regarding simulating IBIS model using Spectre. IBIS model generation always has the die capacitance included and in the generated IBIS file you will have this value as “C_comp”...
View ArticleDesign variable in assember -> copy from cell view issue
Hello,I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9In fact, I set the value of variable (e.g., AAA =...
View ArticleWrong Constraint Values in Sequential Cell Characterization
Hi,I am trying to characterize a D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). This is a positive edge triggered D flip flop based on true-single-phase clocking scheme....
View ArticleHelp!!, Spectre error: Illegal library definition found in netlist for TSMC...
Dear All,When I want to start simulation with spectre the error says:Fatal error: Illegal library definition found in netlistI set the model file correctly, but I don't know why it errors!I opened the...
View ArticleImporting a capacitor interactive model from manufacturer
Hello,I am trying to import (in spectre) an spice model of a ceramic capacitor manufactured by Samsung EM. The link that includes the model is here...
View ArticleUltrasim does not converge with BSIMBULK model
Hello,I am using ultrasim Version 18.1.0.314.isr5 64bit 03/26/2019 06:33 (csvcm20c-2).When I run my netlist, ultrasim is blocked in the first DC stage and takes forever. Then it will fail or never...
View ArticleDifferent Extracted Capacitance Values of the Same MOM Cap Structures...
Hello, I am using Virtuoso 6.1.7. I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High”...
View ArticleERROR (OSSGLD-18): and not able to run simulation
I put some stimulus in the simulation file section : _vpd_data_enb (pu_data_enb 0) vsource wave=[0 0 1n 0 1.015n vcchbm 3n vcchbm] dc=0 type=pwl_vpu_data_enb (pd_data_enb 0) vsource dc=pu_enb type=dcI...
View ArticleDelay Degradation vs Glitch Peak Criteria for Constraint Measurement in...
Hi,This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence...
View Article