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LDO design and simulation
I want to ask about simulation procedure of a digital LDO , how in a feedback it can be simulated? What are the initial condition that need to be given for successful simulation while iterating in...
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How do make the clock 25% duty cycle with jitter capability
How do make the clock 25% duty cycle. I am looking for creating 25% duty cycle ( or a certain High pulse width ) clock where I can add random and deterministic jitter. Hi Andrew,My apology for not...
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Using DFT to analyze a time-interleaving track and hold circuit
Hi,I am evaluating the frequency response and linearity of a time-interleaving track and hold circuit.The input signal frequency can be up to 28GHz, and the sampling frequency (Fs) is 7GHz.In my test...
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Dynamic temperature variation of a SPECIFIC component during transient...
I know how to do dynamic temperature variation during transient simulation and plot temperature as well as any parameters vs time.But what if I want to keep temperature of ALL components to some fixed...
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Pass veriloga parameter to parameters in ADE XL
I'm working on a circuit which requires long transient simulations for a part of the circuit to settle, and I am therefore trying to utilize the State File options of spectre.I save the state at a...
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Pnoise vs Transient noise
Hello!I am simulating the noise effect on an opamp output. The output is buffered so I used both pnoise and transient noise to calculate the rising jitter rms of the output signal. My problem is that...
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How to measure the performance of a PLL ?
Hi, I recently built up a CMOS PLL circuit . And so far, in the trans simulation, it would be stable (locked to reference frequency) after a few uS.My questions are :1. What kind of simulations would...
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Verilog-A Simulation
Hey All,I have just started using verilog-a, and i am trying to simulate the V-I characteristics for a resistor, on DC sweep i neither get any output nor any error message, could anyone help me out...
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Improving Virtuoso Speed
Hi,I'm unsure if this is a concern for the Support, but the setup we use with virtuoso (ICADVM18) is pretty slow. I need to wait a few seconds for every window to open, a time during which I can see...
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Can I analyze LDE effects on finfet design using GPDK cds_ff_mpt_v_0.5
hello. I want to measure the effects of layout dependent effects of analog circuit design (opamps) using finfet technology. I do have access to cds_ff_mpt_v_0.5 GPDK but in the description of this GPDK...
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CDF Parameters: No master specified for instance when running simulation
I've created a simple NOR gate. I want to be able to adjust the width and scaling factor of the NMOS and PMOS transistors in the circuit. Therefore, I have gone ahead and given them the following pPar...
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Difference in gm and Id values obtained in hand calculation and simulation...
Hi,I simulated a nmos in 180nm technology and found its parameters. The hand calculated values for gm and Id were not same as simulated values (different Vgs values were used).Specs: Vdd = 1.8V;...
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assign a sub list to the range of nested foreach loop
I would like to use Ocean to group a few corner cases to a single plot after ADE XL corner sim. For example, I have these corner numbers (for fetching tran analysis results), and I could group them...
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Ascending to top level when a simulation is run
I’ve noticed that when I run a simulation using ADE Explorer, it automatically ascends to the top level of the simulation testbed. This is not always desired. For example, if you are looking at DC...
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pnoise jitter Jee plot button disappeared
Hi everyone,With ADEXL, in a shooting pss + pnoise jitter analysis, I try to plot the jitter (edge) Jee vs. df, but the "plot" button has disappeared! I can only get the integrated noise value; I was...
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Eldo netlist generation with ADE L.
Hello,I try to generate an Eldo netlist from ADE L. I configure the simulator to EldoD, but i got this error:ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'eldoD...
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How to install PVS
Hello, please tell me if I can install PVS separately for Cadence. What commands do I need to use for this?
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Spectre: possible to use netlists for subcircuits in ONLY selected blocks?
Hi! Is it possible to instruct Spectre to use netlists for subcircuits in only some blocks of a hierarchy, and other views (e.g. schematic) elsewhere?Our foundry supplies netlists with extracted RC...
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Segmentation fault in a PSS simulation (ADE-XL)
Hi Andrew/someone,I have a testbench in ADEXL (a PSS simulation) that returns a segmentation fault.I am said to "submit the case via Cadence Online Support", could you please explain to me exactly the...
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How to add a new component-part in Virtuoso
Hi ,I have this spice code from ALADIN website, it is supposed to be the spice file for two nmos transistors connected in a certain way in one chip as in the attached figure.I want to create this new...
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