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Current annotation on the symbol
I am using IC6.1.7 and want to annotate DC voltages and currents on the symbol itself. While generating the symbol, under "Symbol Generation Options" I tick Load/Save then select "analog" from the drop...
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Difference between dft and the Spectrum
Dear Sir, I would like to ask you please what is the difference between the dft function from the calculator and the Spectrum tool provided by ADE, I want to simulate the THD and the SNR of my...
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Transient Noise Analyses in Cadence
Dear Sir,I would like to ask you please what is the difference between the normal transient analyses and the transient noise analyses ? , for me I presume that that even normal transient simulation can...
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Stochastic-mismatch model in Verilog-A
Hello cadence community,I have a question about adding models when trying to set up an MC simulation. I will be clear enough in what i'm doing:1| I have my Verilog-A model working with no problems in...
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Alter statement usage for trimming (reelaborate card)
Hi all!I'm exploring the potentialities of alter statement and I found the re-elaborate option (boolean type), which basically re-elaborates the circuit and trigger the expression evaluation in the...
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WHICH SkillAPI can perform (ADEL)config view -> File -> Save Cell Table Data
I want to AUTO export all extract_view list from current working config view,then use bash script to AUTO re-extract ALL post layout view for better efficient.The question is after I perform "config...
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Virtuoso flatten verilog netlist generation question
Hi,Since some sw does not understand the bus type instance format, I would like to have a flattened Verilog netlist.Is there an option to generate flattened verilog netlist?(Current output)buffer...
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Monte Carlo Simulations: Defining Standard Deviation, Mean, Number of...
Hello,I am using Virtuoso version IC6.1.7.I run a Monte Carlo simulation, with let's say 100 iterations. Then I calculate a scalar output, let's say offset voltage, and get an histogram.1) How can I...
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nlSetPcellName for a resistor
Hi Andrew:I had lines below in a libInitCustomExit.il file;; Adds a random number and time-stamp to the end of the mdoule name of subcircuits.pcellNameTable = makeTable("PcellNameTable" nil)procedure(...
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CDL syntax error
Ive created a Pcell that instantiates a PDK resistor and added a well tap. I can netlist using ansCdlHnlPrintInst .SUBCKT resTest minus nwell plus *.PININFO minus:I nwell:I plus:I RR0 rpodwo R=655 M=1...
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deepprobe to a bussed net in AMS
Hi,I'm trying to use a deepprobe instance from analogLib to probe a bused net inside one of the circuits in an AMS simulation. I found some rather old posts on this issue (deepprobe with AMS) and...
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How to rename copy library with prefix/suffix added in all the cells
Hello, I saw some of the posts regarding this issue. But, most of them are dormant for some time and I have some unique requirements:1. The code should allow me to replace existing prefix with the new...
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How to measure deterministic jitter from eye-diagram by using command
Dear All,I want to measure deterministic jitter from eye-diagram by using command.Manually, using cursors one can measure the deterministic jitter (DJ) manually. But for doing this across corner is...
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Issues with using abEyeCross.il (giving WRONG results when compared to...
Dear All, I am using abEyeCross.il from solution 11395772(https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nX0ZEAU&pageName=ArticleContent).This is to find peak-to-peak...
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Modelfile not loaded in ADE
I transferred an existing project with PDK into our environment.In .cdsinit it is set: envSetVal("spectre.envOpts" "modelFiles" 'string "/model_libraries/models/lvt_mos.scs;TT")When verifying in the...
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How do I parameterize analoglib.ipwlf's cdf parameter"PWL file name"
The situation is different PWL file for different cornerI want to parameterize analoglib.ipwlf's cdf parameter by fill "FILEPATH"/VAR("FILEPATH")/VAR(FILEPATH)then I set variable combine with corner...
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Backwards Time Simulation to Determine Boundaries of Convergence
Is it possible to run a backwards time simulation in Virtuoso 6.1.7?I am trying to find out how far from an equilibrium I can set the initial conditions of a circuit's nodes and still have them...
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how to short circuit in layout for analogLib\iPRB kind behavioural cell
hello experts,I noticed from other post that lxRemoveDevice which can remove devices and short in the process. but that's some script to process while netlisting. can we set some property in the...
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Updating a PDK technology layermap and technology
Hi.We're trying to update one of our PDKs at lab to contain the latest Layout Editor information.We received from the vendor a .map file and a .tf file, and I would like to verify that we are updating...
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Standard Cell Library Integration
Hi, New to Cadence tools and I am not sure how to integrate a PDK standard cell library into Virtuoso for schematic design and layout. I have the libraries imported and can view the symbol and...
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