Virtuoso flatten verilog netlist generation question

Hi,

Since some sw does not understand the bus type instance format, I would like to have a flattened Verilog netlist.

Is there an option to generate flattened verilog netlist?

(Current output)

buffer I0[1:0] ( .Z(net0_1_, net0_0_), .I(net1_1_, net1_0_));

(Desired format)

buffer I0_1_ ( .Z(net0_1_), .I(net1_1_));

buffer I0_0_ ( .Z(net0_0_), .I(net1_0_));

Regards,