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EMIR simulation fails with DSPF-114 code
Hi,I am trying to run EMIR analysis on a mixed-signal design. The digital part has been verified separately, so when I did LVS in preparation for QRC extraction, I included the digital block's name in...
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Spectre.hbnoise warning
HelloI am using virtuoso custom IC design environment version IC6.1.7-64b.500.12.Somehow when at startup the configuration variables are loaded from .cdsenv, it issues the following warning...
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Howto generate a ibis model from schematic/extracted design
Hi,is there any tutorial that explains how to generate an IBIS model in Virtuoso 6.1.7. ?I do have a CML output buffer and want/need to generate an IBIS model.As I have never done that before I am...
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ymax on a waveform family
Hi Everyone,I've had some nested sweeps in spectre, which resulted in waveforms families in OCEAN. ymax() does not work on some of my waveform families, but works on other ones. What could cause it?...
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Ocean script running on Centos6 but not on Centos7
Hi. I have an ocean script that runs on C6 fine, but hangs on C7. It's invoked from a python environment, and I'm trying which of the following goes wrong:1. Python script2. Ocean simulation files3....
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How to export schematic images for all the cellviews in a config at once
I have a project with a lot of different (nested) cell views.I would like to print out images of all the used cell views (in the config file).I've found some settings for 'Export Image...' that works...
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How to load bare virtuoso?
Hi EveryoneI remember there is an option during the virtuoso launching to skip loading the in-house wrapper and content inside the .cdsinit* files.Besides, it's also possible to skip loading such...
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Global optimization over several corners - question
Hi,I'm using Global Optimization in ADE Assembler and would like to change what appears to be the default behaviour.I have a number of corners - 3, in the present case. For each corner, I have a...
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Bind key for setting to "copy reference" mode in the "Quick Align" window.
Hi,I am looking to assign a bindkey to switch between enabling and disabling "Copy Reference" in the "Quick Align" window in "Virtuoso Layout". Could you please provide a procedure, that I can tag to...
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setting a group of dynamic parameters every 1ms
hi Andrew,thanks for your quick reply to my question regarding "setting a group of dynamic parameters every 1ms". i still got some confusions:1. my actual use case is to change a group of register bit...
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CDS.log problem
Hi,I have a problem with CDS.log file.When I run ADEXL sims with large number of corners, I noticed that the CDS.log file size increases significantly, several GBs. sometimes when disk is not...
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The effective CDF data for the following objects differs from their base CDF...
Hello,The message "the effective CDF data for the following objects differs from their base CDF data" always display when refreshing the library manager. The situation occurs after a hierarchical...
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ViVA: Post processing CSV file
Hi,We are doing a spice simulation, after settling the voltage value at particular net, we clipped that value between the settled point (say 9u to 10u)Now, I want to give this as stimuli to other...
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How to increase X axis and Y axis limit in layout
HI all, While creating layouts I am getting the following error\w *WARNING* (DB-270547): The coordinate 2.14907e+09 is over the max 2.14748e+09 and 2.14748e+09 is used. . is there an option to...
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Layout pcell label tinkering
I've been slowly working my way towards making Virtuoso work with everything on a white background. On the layout side I have an issue with instantiated pcells that I'm using (I didn't make them) -...
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Updating Net Names in Layout XL
I'm having trouble getting the update components and nets function to work as I expect in Layout XL. I'm creating several flavors of a ring oscillator and instead of starting from scratch I copy the...
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ihdl vs netExpr
I have a question about inherited connections and ihdl. Short version is ihdl adds a "!" to the terminal db object name in the generated schematic and I didn't expect the "!" there.According to the...
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Possible to launch Virtuoso and close the terminal without killing it?
Hi! I am looking for a way to launch virtuoso from a csh terminal, in a way that it won't be killed if I (usually accidentally) close the terminal. I triednohup virtuoso &but this doesn't work....
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Simulation for Ferroelectric Capacitor (Based on VerilogA model) for C-V curve
Hi,I have created a Ferroelectric Varactor model using VerilogA. Now, I wan to simulate the C-V curve. I have added a voltage source with the varactor with AC magnitude of 1. Now for ac analysis, I...
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Layout editor: quick align "Move/Stretch" mode deprecated in ICADV?
Hi! The "Move/Stretch" mode is not available in my layout editor (L) in ICADV 12.3. Here's a comparison of what I see in IC 6.1.6 (28nm PDK, left) and ICADV 12.3 (16nm PDK, right):Moreover, the Layout...
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